Title:
METHOD FOR MANUFACTURING CAPACITANCE CONNECTION LINE OF MEMORY, AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2022/095609
Kind Code:
A1
Abstract:
Provided in the present disclosure are a method for manufacturing a capacitance connection line of a memory and a memory. The manufacturing method comprises: sequentially forming a bit line layer and a first dielectric layer on a substrate; patterning the bit line layer and the first dielectric layer, and forming bit line structures arranged at intervals along a first direction and dielectric structures positioned at top parts of the bit line structures; forming an insulation layer on the substrate where the bit line structures and the dielectric structures are formed, so as to completely cover the bit line structures and the dielectric structures; forming second isolation structures arranged at intervals between adjacent bit line structures; forming an electrical conduction structure between a first isolation structure and a second isolation structure, and forming a storage node contact structure.
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Inventors:
CHEN YANG (CN)
Application Number:
PCT/CN2021/118675
Publication Date:
May 12, 2022
Filing Date:
September 16, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L27/108; H01L21/8242
Foreign References:
| CN107275286A | 2017-10-20 | |||
| CN107230675A | 2017-10-03 | |||
| CN111192876A | 2020-05-22 | |||
| US20140154863A1 | 2014-06-05 |
Attorney, Agent or Firm:
BOXIN CHINA INTELLECTUAL PROPERTY (CN)
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