Field of the invention

The invention is in the field of integrated circuitry and transducers in particular of complementary metal oxide silicon application specific integrated circuits (CMOS ASIC and its derivatives) and integrated micro electro mechanical devices and systems (iMEMS), in particular transducers containing CMOS circuitry.

Background of the invention

CMOS is the most used technology for very large scale integrated circuits (VLSI circuits). Micro electro mechanical devices (MEMS) applies to a broad family of micro-machined transducers, sensors, actuators and systems with coupled electrical, mechanical, radiant, thermal, and chemical effects. The term iMEMS refers to silicon integrated MEMS based on IC technology combined with micro-machining, film deposition or electroplating [1].

Interference of electrical signals in integrated circuits can substantially limit the accuracy. Thermal effects caused by on-chip temperature gradients or variation of the environmental temperature may cause problems in analog circuitry or transducers. Packaging and intrinsic stress of CMOS devices and transducers affect the properties of active (e.g. transistors) and passive (e.g. resistor) devices. Sophisticated layout and compensation techniques are applied to reduce these effects. Among these are e.g. fully differential architecture for signal conditioning circuits (reduces electrical interference), low stress packages (reduces packaging stress) or heating of the complete chip to a fixed temperature (reduces temperature related effects).

Recently, novel methods for overcoming such problems have been reported. For example, the noise sensitive part of a circuit can be separated from the noisy part of it by narrow grooves or trenches etched into the substrate from the back of the wafer by anisotropic etching. For stability reasons such grooves cannot surround the sensitive part completely and therefore the de¬ coupling effect is not satisfactory in many cases.

For thermal isolation of structures, it is known to remove locally the whole bulk of the substrate by anisotropic etching from the back of the wafer, reducing it locally to a mere Si0 ₂ membrane, on which simple stni4Ctures are fabricated [2]. Similar techniques using anisotropic etching and a chemical etch stop [3] are used from the front of the wafer for electric and/or thermal decoupling of structures based on silicon (n-well) and SiO _z , the etch stop acting on the junction between the p-substrate and the n-well [4, 5]. However, in both cases the decoupled structures are simple and cannot contain e.g. CMOS circuitry, neither digital nor analog.

For producing membrane sensors and actuators (e.g. pressure sensors) [6], anisotropic etching from the back of the wafer is applied to a wafer with an n- epitaxial layer, an electro-chemical etch stop acting on the junction between substrate and epitaxial layer. As this junction extends uniformly over the whole wafer, etching is restricted to one depth. Wafers with epitaxial layers are substantially more expensive than wafers without an epitaxial layer. No CMOS circuitry is available in this technology.

The object of the invention is to overcome the restrictions imposed by the above mentioned methods, i.e. the object of the invention is to create a method for producing on a chip micro-structures with a non limited circuitry, in particular with CMOS-circuitry (digital or analog), whereby it is to be possible to decouple the micro-structures (electric, thermal, and mechanical decoupling) from the rest of the chip in a manner suitable to any specific application. In other words it is the object of the invention to omit the restrictions put on the circuitry by known methods for decoupling micro- structures and to omit the restrictions put on decoupling by CMOS circuitry.

Summary of the invention

According to the invention at least part of a CMOS circuit is decoupled from the bulk of the substrate by positioning this at least part of the CMOS circuit on a secondary substrate with considerably less bulk than the original substrate and by decoupling the secondary substrate at least partly from the original substrate. This is realized by a combination of multi-well technology

and etching with electro-chemical etch stop either from the back or from the front of the wafer (e.g. anisotropic etching). A multi-well is a region consisting of a well diffusion (p- or n-doped) which at least partially contains at least one further well diffusion.

The inventive method comprises the following steps:

On one side of a silicon substrate at least one multi-well structure is produced, the multi-well structure comprising a deep well with a further well positioned inside it or with a further multi-well structure positioned inside the deep well, whereby the further multi-well structure comprises a further deep well and so on. Thereby, the deep well or one of the further deep wells of the multi-well structure is designed for the function of the secondary substrate.

An integrated CMOS circuit with at least parts to be decoupled is produced such that the parts to be decoupled are positioned on the at least one multi-well structure.

The secondary substrate is then decoupled from the substrate by removing by etching at least parts of the substrate below the deep well of the multi-well structure or by removing the well below the one well of a further multi-well structure which has been designed as secondary substrate. Thereby, an electro chemical etch stop is used.

Such electro chemical etch stop works on any p-n-junction, i.e. between the substrate and the deepest well of the multi-well structure or on any junction between wells inside the multi-well structure. This means that the shape of

the multi-well structure is determined not only by the circuitry to be realized but also by the decoupling effects to be achieved for the micro-structure to be realized. In the etching step at least part of the secondary substrate is de¬ coupled from the rest of the chip.

Multi-well structures are per se known from high voltage CMOS processes [7]. For high voltage isolation purposes source and/or drain diffusion (p- or n- doped) of CMOS transistors are placed in additional wells with opposite doping. In order to produce symmetrical pMOS and nMOS high voltage transistors on e.g. a p-doped substrate a p-doped well inside a n-doped well is needed. This special feature of a high voltage CMOS process is according to the invention used for being able to realize electrical, thermal and stress de¬ coupling low voltage CMOS circuits.

In a first step of the inventive method, a wafer is fabricated which contains at least one area with a multi-well structure, which area may contain CMOS or bipolar circuitry or transducers and which area represents the area to be decoupled from the rest of the chip or to be micro-machined. In a second step, the chip or wafer is etched from the front or from the back in order to at least partly free the part of the multi-well structure designed as secondary substrate from the rest of the substrate such effecting the decoupling or realization of the desired structure. The part of the silicon to be removed is basically defined by the multi-well (p/n-junctions), by the crystal orientation of the wafer (e.g. 100 orientation), by the etchant (e.g. KOH, EDP or TMAH) and by the etch mask on the back (for back etching) or on the front of the wafer (for front etching).

All wells of the multi-well structure can be arbitrarily shaped. The multi-well can be considered e.g. as a substrate for a CMOS process which may contain n-MOS devices based on n ⁺ and p ⁺ diffusions in a p-well and p-MOS devices of p ⁺ and n ⁺ diffusions in an n-well.

The major advantages achieved with the inventive method compared to known methods for decoupling parts of integrated circuits are the following:

- The inventive method makes it possible to at least partially electrically, mechanically and thermally decouple CMOS and/or bipolar circuitry and/or transducers on micro-structures from the bulk of the substrate.

Arbitrarily shaped micro-structures containing CMOS devices (open or closed micro-structures) can be fabricated.

No epitaxial layer is required, which may lead to significantly lower production cost of micro-transducers.

Brief description of the Figures

Figure 1 shows a cross section of an exemplified CMOS-chip with a multi- well structure (product of the first step of the inventive method);

Figure 2 shows an exemplified setup for electro chemical etching (second step of the inventive method);

Figures 3 to 7 show examples of micro-structures produced with the inventive method;

Figures 8 and 9 show examples of micro-structures produced with the inventive method comprising removed wells;

Figure 10 shoes a simplified schematic of a magnetic sensor which is positioned on a secondary substrate being thermally, electrically and mechanically decoupled from the bulk of the substrate.

Description of the preferred embodiments

Figure 1 shows an exemplified cross section of a CMOS chip (product of the first step of the inventive method). This chip comprises e.g. a p-substrate 1 and a multi-well structure consisting of wells 2 (n-doped), 2a (p-doped), 2b (n- doped) and 3 (p-doped). Thereby any one of the wells 2, 2a and 2b may be designed to take over the function of the secondary substrate i.e. to be freed at least partially from the bulk of the substrate by removing by etching the substrate and/or the well below.

P-wells and/or n-wells of the chip according to Figure 1 may contain p ⁺ and/- or n ⁺ regions 4 (contact diffusions). Together with additional layers 5 (e.g. gate oxide, polysilicon, metal) n-MOS and p-MOS transistors are fabricated in the multi-well.

In this example the back of the wafer is prepared by an etch mask 6 (e.g. Si ₃ N ₄ ) for subsequent etching from the back.

A setup similar to the one shown in Fig. 2 is used to produce micro-structures by etching from the back of the wafer (second step of the inventive method). The chip or wafer surface is mechanically protected from the etchant 8 (e.g. KOH) by a chip holder or wafer holder 7. A potentiostat 9 controls the potential of the multi-well (2,3) and the bulk 1 of the chip or wafer relative to the etchant by means of a Pt-counter-electrode 10 and an Ag/AgCl reference electrode 11.

Obviously it is possible to use the same setup also for time-limiting an etching process or to reduce the thickness of a secondary substrate after removing the substrate or well below it using an electro chemical etch stop by a further time-limited etching step.

Exemplified schematics of micro-structures produced with the inventive method are shown in Figures 3 to 7. Figure 3 shows a multi-well 2, 3 freed from the back of the chip by removing parts of the substrate 1. Bulk silicon is removed not only below but also beside or around the multi-well whereby the etching is stopped at the lowest CMOS layer 18 (e.g. Si0 ₂ ). This enables thermal electrical and mechanical decoupling from the bulk substrate 1. When suspending the secondary substrate on the dielectric layers 18/19 only, it is adviseable to produce these layers such that they have low internal stress. A method for producing such layers is described in [9].

Figure 4 shows a micro-structure etched from the front. Etching starts through an arbitrarily shaped hole 12 in the dielectric layers. In Figure 5 the multi-well 2/3 is only partially freed by the etching step. This leads to a membrane consisting of the multi-well 2/3 (secondary substrate).

Figure 6 shows a multi-well 2/2a/2b/3 structure according to Figure 1 in which the well 2a is designed as secondary substrate. Again, the secondary substrate is only partially freed by the etch step, whereby the etch stop is performed not at the deepest well but at the junction between wells 2 and 2a within the multi-well structure. This leads to a membrane consisting of the multi-well 2a/2b/3.

Figure 7 shows a cantilever beam formed by a secondary substrate 2/3 which cantilever beam is produced by etching from the front. In order to make the cantilever beam freely movable, the opening 12 where the dielectric layers (18, 19) are interrupted also, surrounds the most part of the beam.

The cross sections shown in Figs. 3 to 7 may be different cross sections of one single micro-structure. All wells and substrates in the drawings are assumed to be connected by p ⁺ and/or n ⁺ regions 4 and metal lines to the outer world.

Parts of integrated circuits may be decoupled for active or passive functions and may serve the following purposes:

Examples for passive function of the decoupling:

electrical decoupling of circuitry or transducers for reducing electrical interference affecting their performance;

thermal decoupling for decoupling circuitry or transducers from on-chip temperature gradients;

mechanical decoupling of decoupled circuitry or transducers for minimizing the effect of induced or intrinsic stress due to packaging.

Examples for active function of decoupled parts:

electric decoupling for control of substrate current of decoupled circuitry or transducer;

thermal decoupling for keeping decoupled circuitry or transducer at a constant temperature by means of a heater;

mechanical decoupling for realizing micro-structures which can be mechanically excited by means of circuitry.

In addition, fabrication of novel micro-structures are feasible by applying the described method to selectively remove part of the multi-well structure. Examples are shown in Figures 8 and 9.

In the structure according to Figure 8, part of the bulk substrate 1 and part of the multi-well structure are removed. Before etching, the multi-well e.g. consists of an n-well 2 which contains p-wells 3. After etching away part of the

substrate 1 and one of the p-wells there is the n-well 2 serving as secondary substrate and a tunnel 13 between the CMOS layers 5 and the n-well 2.

Figure 9 shows a further chip produced according to the inventive method. Before etching it comprised a multi-well structure with three wells (2, 2a, 3), whereby the deepest well was designed to be etched away and the well 2a just above the deepest well was designed as secondary substrate. Etching from the front side of the chip results in a tunnel 13 below the secondary substrate. The bulk of the substrate 1 is left untouched.

An example of an electrically, thermally and mechanically decoupled micro- structure is given in Figure 9. It is a magnetic sensor 14 (Magnetotransistor [8]) which is realized on secondary substrate 2 freed by anisotropic etching using an electro chemical etch stop.

Stress which is induced on the sensor by packaging is minimized due to mechanical decoupling from the substrate 1. The temperature of the sensor is kept constant by means of a temperature sensor 16 and a heater 15 on the micro-structure which makes it possible to cancel effects due to changing environment temperature. On-chip circuitry 17 may be realized on-chip.

References

[1] H. Baltes, "Integrated Micro Electro Mechanical Systems", Elektrotechnik und Informationstechnik, vol. 112, pp. 488-492, 1995.

[2] R. Leggenhager, "CMOS Thermoelectric Infrared Sensors", Ph.D. Thesis, No. 10744, ETH Zurich, Zurich, Switzerland, 1995.

[3] B. Kloek, S.D. CoUins, N.F. de Rooij, R.L. Smith, "Study of Electro¬ mechanical Etch-Stop for High-Precision Thickness Control of Silicon Membranes", IEEE Transactions on Electron Devices, Vol. 36, No.4, pp. 663-669, 1989.

[4] R.J. Reay, E.H. Klaassen and G.T.V. Kovacs, "A Micromachined Low- Power Temperature-Regulated Bandgap Voltage reference", IEEE Journal of Solid State Circuits, Vol. 30, No. 12, 1995.

[5] E.H. Klaassen, R.J. Reay, C. Storment, J. Audy, P. Henry, A.P. Brokaw and G.T.A. Kovacs, "Micromachined Thermally Isolated Circuits",

Technical Digest of Solid-State Sensor and Actuator Workshop, USA, pp. 127-131, 1996.

[6] M. Hornung, R. Frey, O. Brand, H. Baltes, C. Hafner, "Ultrasonic Barrier Based on Packaged micromachined Membrane Resonators", Proc. IEEE

MEMS'95, pp. 334-339, 1995

[7] Austria Mikro Systeme, "High Voltage CMOS Process", AMS Data Sheet, Unterpremstatten, Austria, 1996.

[8] A. Haberli, M.Schneider, P. Malcovati, R. Castagnetty, F. Maloberti, H. Baltes, "2D Magnetic Microsensor with On-Chip Signal Processing for Contactless Angle Measurement", IEEE Int. Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 332-333, 1996.

[9] U. Munch, D. Jaeggi, K. Schneeberger, A. Schaufelberger, O. Paul, H. Baltes, J. Jasper, "Industrial Fabrication Technology for CMOS Infrared Sensor Arrays", Proc. Transducers '97 Intl. Conf . on Sol. State Sensors and Actuators, Chicago, June 16-19, 1997.