Title:
MULTI-LAYER WIRING BOARD
Document Type and Number:
WIPO Patent Application WO/2014/181697
Kind Code:
A1
Abstract:
The present invention provides a technology capable of achieving a smaller surface area and narrower pitch for mounting electrodes which are disposed on one surface of a laminate and to which specific components are connected, and provides technology capable of reliably forming a plating coating on the mounting electrodes configured to occupy little surface area. Since each mounting electrode (10a to 10i) for connection to a specific component is formed from one end surface of a respective first via conductor (20), a smaller surface area and narrower pitch can be achieved for the mounting electrodes (10a to 10i). In addition, since each mounting electrode (10a to 10i) formed from the one end surface of a respective first via conductor (20) is connected by an internal wiring electrode (30) to a planar electrode (ANT; Pin; GND; Vin; 11a to 11c; and 12) formed on an end face of a second via conductor (21) exposed on the surface of the laminate (100), a plating coating can be reliably formed on the mounting electrodes (10a to 10i).
Inventors:
KITAJIMA HIROMICHI (JP)
Application Number:
PCT/JP2014/061525
Publication Date:
November 13, 2014
Filing Date:
April 24, 2014
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H05K3/46; H01L23/12; H05K3/34
Domestic Patent References:
| WO2012132762A1 | 2012-10-04 |
Foreign References:
| JP2012104774A | 2012-05-31 | |||
| JP2008066712A | 2008-03-21 | |||
| JP2004297456A | 2004-10-21 | |||
| JP2013026583A | 2013-02-04 | |||
| JP2006080333A | 2006-03-23 | |||
| JP2007115952A | 2007-05-10 |
Attorney, Agent or Firm:
YANASE, Yuji et al. (JP)
Yuji Yanase (JP)
Yuji Yanase (JP)
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