Title:
PHASE SYNCHRONIZATION CIRCUIT, PHASE SYNCHRONIZATION METHOD AND COMMUNICATION DEVICE
Document Type and Number:
WIPO Patent Application WO/2017/043254
Kind Code:
A1
Abstract:
This phase synchronization circuit is provided with: a detection unit that detects transition of an input clock signal; an oscillation unit that generates a clock signal having a frequency corresponding to a first control signal and changes the phase of the clock signal on the basis of the result of detection by the detection unit; an adjustment unit that adjusts a phase difference between the phase of the input clock signal and the phase of the clock signal according to a second control signal; and a control unit that compares the phase of the input clock signal and the phase of the clock signal at a plurality of comparison timings, and generates the first control signal and the second control signal on the basis of the comparison results thereof.
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Inventors:
MASUDA TAKASHI (JP)
Application Number:
PCT/JP2016/073817
Publication Date:
March 16, 2017
Filing Date:
August 15, 2016
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H03L7/083; H03L7/08; H03L7/081; H03L7/087
Domestic Patent References:
| WO2016152438A1 | 2016-09-29 |
Foreign References:
| JP2014187561A | 2014-10-02 | |||
| JP2013118638A | 2013-06-13 | |||
| US8841948B1 | 2014-09-23 |
Other References:
QUENTIN BERAUD-SUDREAU ET AL.: "SiGe Clock and Data Recovery System Based on Injection-Locked Oscillator for 100 Gbit/s Serial Data Link", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 49, no. 9, September 2014 (2014-09-01), pages 1895 - 1904, XP011557104
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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