Title:
POWER SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2017/217369
Kind Code:
A1
Abstract:
This power semiconductor device comprises an insulating substrate that has a conductor layer at least in the front surface, a wire bump that is provided on the conductor layer, a semiconductor element that is disposed on the wire bump, and a solder layer that bonds the semiconductor element onto the conductor layer, and/or comprises a base plate, a plurality of wire bumps that are provided on the base plate, an insulating substrate that is disposed on the wire bumps and has a conductor layer at least in the back surface, and a solder layer that bonds the conductor layer of the insulating substrate onto the base plate. This power semiconductor device has an alloy at the interface between each wire bump and the solder layer, said alloy being composed of the materials of the wire bump and the materials of the solder layer.
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Inventors:
YANAGIMOTO TATSUNORI (JP)
ASADA SHINSUKE (JP)
TOKUBO KOICHI (JP)
ASADA SHINSUKE (JP)
TOKUBO KOICHI (JP)
Application Number:
PCT/JP2017/021649
Publication Date:
December 21, 2017
Filing Date:
June 12, 2017
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H01L21/52; H01L21/60; H01L23/36; H01L23/40; H01L25/07; H01L25/18
Domestic Patent References:
| WO2010147187A1 | 2010-12-23 |
Foreign References:
| JPH11186331A | 1999-07-09 | |||
| JP2005236019A | 2005-09-02 |
Attorney, Agent or Firm:
SAMEJIMA, Mutsumi et al. (JP)
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