Title:
PREPARATION METHOD FOR POLYIMIDE VIA AND WAFER LEVEL SEMICONDUCTOR PACKAGING STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2024/045732
Kind Code:
A1
Abstract:
The present invention provides a preparation method for a polyimide via, and a wafer-level semiconductor packaging structure. The preparation method for the polyimide via comprises: S1: providing a substrate having a metal pad attached to a surface; S2: forming a polyimide layer on the substrate; S3: forming a metal layer on the polyimide layer; S4: forming a preset layer on the metal layer, and forming a first pre-via on the preset layer; S5: etching the metal layer to form a second pre-via; S6: etching the polyimide layer to form a third pre-via; S7: removing all structures on the polyimide layer, so as to form a polyimide via on the polyimide layer. The present invention avoids the problem of residue remaining at the bottom part of a small-sized polyimide via, ensuring a basically consistent top-to-bottom contour of the polyimide via, and the preparation process is refined, thereby improving product yield. In wafer-level semiconductor packaging, a relatively small polyimide via can allow for more intricate and detailed product designs, significantly improving chip performance.
Inventors:
LIU XIANG (CN)
YIN JIASHAN (CN)
ZHOU ZUYUAN (CN)
XUE XINGTAO (CN)
LIN CHENGCHUNG (CN)
YIN JIASHAN (CN)
ZHOU ZUYUAN (CN)
XUE XINGTAO (CN)
LIN CHENGCHUNG (CN)
Application Number:
PCT/CN2023/097808
Publication Date:
March 07, 2024
Filing Date:
June 01, 2023
Export Citation:
Assignee:
SJ SEMICONDUCTOR JIANGYIN CORP (CN)
International Classes:
H01L21/48
Foreign References:
| CN115132591A | 2022-09-30 | |||
| US4536249A | 1985-08-20 | |||
| JPH05275856A | 1993-10-22 | |||
| CN111952169A | 2020-11-17 | |||
| CN103137469A | 2013-06-05 | |||
| CN101566799A | 2009-10-28 |
Attorney, Agent or Firm:
J.Z.M.C. PATENT AND TRADEMARK LAW OFFICE (GENERAL PARTNERSHIP) (CN)
Download PDF: