Title:
SEMICONDUCTOR DEVICE AND METHOD FOR SEMICONDUCTOR DEVICE FABRICATION
Document Type and Number:
WIPO Patent Application WO/2023/180859
Kind Code:
A1
Abstract:
The present invention has a first memory cell, a second memory cell on the first memory cell, a first conductor, and a second conductor on the first conductor, the first memory cell and the second memory cell each having a transistor, a capacitive element, and a first insulator on the transistor, the transistor having a metal oxide, a third conductor, fourth conductor, and second insulator on the metal oxide, a fifth conductor on the second insulator, a third insulator under the metal oxide, and a sixth conductor under the third insulator, the capacitive element having a seventh conductor, a fourth insulator on the seventh conductor, and an eighth conductor on the fourth insulator, the fourth conductor and the seventh conductor being in contact via an opening provided in the first insulator, the first conductor and the second conductor each having a portion in contact with the third conductor, one side end part of the third conductor substantially coinciding with one side end part of the metal oxide, and one side end part of the fourth conductor substantially coinciding with the other side end part of the metal oxide.
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Inventors:
HODO RYOTA (JP)
ENDO TOSHIYA (JP)
NAKANO MASARU (JP)
SAWAI HIROMI (JP)
YAMAZAKI SHUNPEI (JP)
ENDO TOSHIYA (JP)
NAKANO MASARU (JP)
SAWAI HIROMI (JP)
YAMAZAKI SHUNPEI (JP)
Application Number:
PCT/IB2023/052379
Publication Date:
September 28, 2023
Filing Date:
March 13, 2023
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB (JP)
International Classes:
H10B12/00; H01L21/336; H01L21/768; H01L21/8234; H01L23/522; H01L27/06; H01L27/088; H01L29/786; H10B41/70
Domestic Patent References:
| WO2021038361A1 | 2021-03-04 | |||
| WO2020183277A1 | 2020-09-17 | |||
| WO2018178793A1 | 2018-10-04 | |||
| WO2019049013A1 | 2019-03-14 | |||
| WO2021009620A1 | 2021-01-21 |
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