Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/186279
Kind Code:
A1
Abstract:
Provided is a semiconductor device that has a novel configuration. The semiconductor device comprises a plurality of arithmetic operation blocks each comprising an arithmetic operation circuit unit and a storage circuit unit. The arithmetic operation circuit unit and the storage circuit unit are electrically connected. The arithmetic operation circuit unit and the storage circuit unit have mutually overlapping regions. The arithmetic operation circuit unit includes a Si transistor, for example, and the storage circuit unit includes an OS transistor, for example. The arithmetic operation circuit unit has the function of performing a product-sum operation. The storage circuit unit has the function of holding weighting data. A first drive circuit has the function of writing the weighting data to the storage circuit unit. The first drive circuit is used to write weighting data to all storage circuit units included in the same row.
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Inventors:
OKAMOTO YUKI (JP)
ONUKI TATSUYA (JP)
KOZUMA MUNEHIRO (JP)
MATSUZAKI TAKANORI (JP)
ONUKI TATSUYA (JP)
KOZUMA MUNEHIRO (JP)
MATSUZAKI TAKANORI (JP)
Application Number:
PCT/IB2021/051788
Publication Date:
September 23, 2021
Filing Date:
March 04, 2021
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB (JP)
International Classes:
H01L27/088; G06F15/80; H01L21/336; H01L21/822; H01L21/8234; H01L21/8242; H01L27/04; H01L27/108; H01L27/1156; H01L29/786; H01L29/788; H01L29/792
Foreign References:
| JP2019047006A | 2019-03-22 | |||
| JP2019036280A | 2019-03-07 | |||
| JP2015188071A | 2015-10-29 | |||
| JP2019033233A | 2019-02-28 | |||
| JP2012256822A | 2012-12-27 |
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