Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/042809
Kind Code:
A1
Abstract:
A chip-scale package semiconductor device (1) which can be mounted face-down comprises a semiconductor substrate (32), a semiconductor layer (40) formed on the semiconductor substrate (32), a vertical field effect transistor (10) formed on the semiconductor layer (40), ball-type bump electrodes formed on the front surface-side relative to the semiconductor layer (40) and having a height of at least 100 µm, and a metal layer (30) having a multi-layer configuration and being formed in contact with the entire surface of the back surface-side of the semiconductor substrate (32), wherein: a first metal layer (30a) which is the thickest part within the metal layer (30) has a first metal as a main constituent, said first metal having the highest ductility among the metals constituting the metal layer (30); the first metal layer (30a) has a thickness of at least 8 µm; the outer periphery of the metal layer (30) in a planar view of the semiconductor layer (40) is provided with a protrusion (50) which protrudes downward relative to the back surface-side of the semiconductor substrate (32); and in a cross-sectional view of the protrusion (50), there is a section in which the width of the protrusion (50) becomes at least 5 µm.
More Like This:
| WO/2022/061768 | POWER DEVICE AND MANUFACTURING METHOD THEREFOR |
| JPH01256166 | MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
| WO/2001/037345 | RADIATION RESISTANT INTEGRATED CIRCUIT DESIGN |
Inventors:
NAKAYAMA YUSUKE
TAGUCHI MASAHIDE
TAGUCHI MASAHIDE
Application Number:
PCT/JP2023/020639
Publication Date:
February 29, 2024
Filing Date:
June 02, 2023
Export Citation:
Assignee:
NUVOTON TECH CORPORATION JAPAN (JP)
International Classes:
H01L29/78; H01L21/301
Foreign References:
| JP2020025115A | 2020-02-13 | |||
| JP2008192998A | 2008-08-21 | |||
| JP2021114621A | 2021-08-05 | |||
| JP2020053451A | 2020-04-02 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
Download PDF:
Previous Patent: AUTOMATIC ANALYSIS DEVICE
Next Patent: HEAT INSULATING WALL AND HEAT INSULATING CONTAINER
Next Patent: HEAT INSULATING WALL AND HEAT INSULATING CONTAINER