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WO/2007/129491A1 |
An electronic device for capturing a data signal from an electronic device employing source synchronous clocking. The electronic device comprises a reception circuit for inputting an input data signal and an input clock signal indicating...
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WO/2007/129386A1 |
There is provided a test device for accurately judging the state of an electronic device employed for source synchronous clocking. A first variable delay circuit (210) of the test device delays a data signal outputted from a device (100)...
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WO/2007/126176A1 |
The present invention relates to a fuel booster constructed in such a manner that an externally input voltage is converted to a driving voltage and an operating voltage through a transformer and an SMPS controller and/or a constant volta...
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WO/2007/118050A2 |
A method for sensing voltage on an internal node in an integrated circuit includes applying a voltage larger than a threshold value to a first pad, generating from the activation voltage a potential for a sensing circuit and coupled to t...
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WO/2007/116695A1 |
A data signal generating apparatus that, though having a small-scale structure, can output serial data in a desired sequence without exhibiting an unstable state even for a wide range of data rate and also can support a jitter measuremen...
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WO/2007/116697A1 |
It is possible to provide a waveform shaping device and an error measuring device capable of performing a waveform shaping process at a position where a sufficient amplitude is available for an input data signal even when the input data ...
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WO/2007/116468A1 |
The present invention enables the monitoring of various types of noise included in signals of signal lines on a circuit board and also enables an automatic adjustment of the threshold value for use in a signal state determination with th...
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WO/2007/117918A1 |
A programmable multi-cycle signaling scheme provides synchronous communications over relatively large distances. An input digital data stream is de-multiplexed onto multiple conductors. The digital data stream is recreated at the far end...
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WO/2007/114379A1 |
A variable delay circuit for providing an output signal obtained by delaying an input signal by a designated delay time. The variable delay circuit comprises a delay control part that provides a control voltage in accordance with a set v...
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WO/2007/111035A1 |
A data receiver comprises an amplifying circuit (41) that amplifies a received duo-binary data with a predetermined gain for output; an offset canceling part (56,57) that cancels the offset of an output signal of the amplifying circuit (...
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WO/2007/111611A1 |
A differential circuit (100) is configured to accept a differential excitation voltage (101) across its input terminals (102, 104) and, in conjunction with a pair of capacitive absolute pressure sensors (106, 108), is configured to produ...
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WO/2007/110915A1 |
There are included a peaking determining part that determines a peaking amount of the output part of an inductor peaking circuit; and a control signal generating part that changes circuit parameters of the inductor peaking circuit based ...
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WO/2007/109453A2 |
A current comparator includes an input node for receiving an input current, an output node, a first wide swing current mirror having an input coupled to the input node of the current comparator, a power node for receiving a first power s...
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WO/2007/105153A1 |
A circuit arrangement and method utilize a variable threshold, multi-stage pulse shaping circuit to pulse shape a signal output by a crystal oscillator circuit. Each stage of the pulse shaping circuit includes a Schmitt trigger that driv...
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WO/2007/104534A1 |
The circuit arrangement (1) comprises an input (2) for connecting an oscillator (3) and an amplifier circuit (20) having a first input (21), which is coupled to the input (2) of the circuit arrangement (1), having a second input (22) and...
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WO/2007/101767A1 |
The present invention relates to a method and a data transmission system for transmitting data encoded in a signal (10) between a sending subscriber (14) and a receiving subscriber (36) in the data transmission system via a network struc...
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WO/2007/101824A1 |
An adjusting circuit (100) includes a current-starved voltage-controlled circuit configured to adjust a first type of signal difference. A phase-interpolated voltage controlled circuit (M1 - M8) is configured to adjust a second type of s...
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WO/2007/099079A1 |
The present invention relates to an interface circuit for linking a sensor to a controller, in particular to a motor controller, having at least one signal input (A1) via which a sensor current signal (Is) can be injected, having a curre...
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WO/2007/101014A2 |
A hybrid digital pulse width modulator can have a delay line with digitally programmable delay cells. The digitally programmable delay cells can be adjusted by a digital correction signal from a delay matching circuit.
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WO/2007/101073A2 |
A circuit for transmitting signals includes a transformer having an input side and an output side, the input side having a first end and a second end. A first transistor is coupled to the first end of the transformer, the first transisto...
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WO/2007/100348A1 |
Methods and apparatuses for blind equalizers with multiple constant modules. In one embodiment, a circuit, includes: a filter to produce an output based on an input that represents a symbol being received, the symbol being one of a Quadr...
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WO/2007/093477A1 |
A latch circuit (1) comprising a first input device (10a) in a first branch (4a) and a second input device (10b) in a second branch (4b). The latch circuit comprises a first estimator unit (40a) adapted to generate a first estimate of a ...
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WO/2007/091413A1 |
A change point detection circuit detects a timing of a change point where a logical value of a signal to be measured changes. The change point detection circuit includes: a multi strobe circuit for generating a logical value data string ...
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WO/2007/090261A1 |
A level shifter circuit for converting a logic signal with logic '1' and '0' levels at first high and low supply voltage levels to a signal with second high and low supply voltage levels. In particular, the second high and low supply vol...
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WO/2007/092067A2 |
A receiver (e.g., for a 1OG fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-cha...
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WO/2007/090644A1 |
A circuit arrangement (1) for actuating an electrical load (13) comprises a first connection (2) and a second connection (3) for feeding a first control signal (S1) and a second control signal (S2), a first output (23) to which the elect...
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WO/2007/088211A1 |
The invention relates to a device comprising at least one delay line for applying a variable delay to a clock signal and a controller for controlling the variable delay of the delay line. Each delay line comprises a plurality of concaten...
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WO/2007/086500A1 |
A control signal inputting circuit is provided for supplying control signals to a plurality of circuits to be controlled. The control signal inputting circuit is provided with the N number of control signal storing/outputting circuits, w...
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WO/2007/083443A1 |
A skew correcting apparatus comprises a transition detector (10), when detecting a transition of an input data signal, provides a pulse signal; a variable delay line (20) that generates a first delayed data signal obtained by delaying th...
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WO/2007/080918A1 |
A phase comparison circuit is provided with a fraction divider (31) for forming a fraction divisional signal (Svn) by fraction-dividing a clock signal in response to a control signal from a control circuit (32), a first integer divider (...
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WO/2007/075312A2 |
A phase interpolator includes a first circuit to generate a first signal (PHINO) having a first phase delay and a second signal (PHINl) having a second phase delay and a phase mixer (105). The phase mixer (105) is coupled to receive the ...
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WO/2007/074237A2 |
The invention relates to a method for adjusting a pulse detection threshold consisting in detecting a pulse when the edge of said pulse envelop crosses the threshold, in allocating (A) a staring value (TH0) to the threshold and in adjust...
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WO2006124165B1 |
A programmable modulator (100) is programmable to operate in either of a GMSK or 8PSK mode. When operating in a GMSK mode, a signal modulating circuit 105 receives (210) a bit stream (110), maps the bit stream (110) to a phase value in c...
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WO/2007/072731A1 |
An oscillation circuit which generates an oscillation signal synchronous with given reference clock. The oscillation circuit is provided with a voltage controlled oscillation section, which stops oscillation of an oscillation signal havi...
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WO/2007/072588A1 |
In a comparator for use in a parallel A/D converter, the comparator (100) is provided with reset transistors (mra, mrb). When the comparator (100) is in reset state, the PMOS transistors (mra, mrb) are provided with the inverted signal /...
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WO/2007/069138A2 |
An electric circuit (30) for generating a clock-sampling signal (CLK) for a sampling device (31) comprises a clock generator (1, 40, 50, 60) for generating a plurality of clock signals (21 - 24, 51 - 54, 61 - 64), a correlation device (L...
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WO/2007/069139A2 |
An electric counter circuit (30, 40, 80) comprises a clock generator (1, 54, 111, 120, 130) for generating a plurality of clock signals (21 - 24, 121 - 125, 131 - 134) and a sampling device (32, 81) for sampling the clock signals (21 - 2...
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WO/2007/066456A1 |
An error detecting circuit (180) detects parity errors occurred in analog circuits during the receipt of SYNC and outputs signals sequentially to a circuit-characteristic setting section of a digital circuit (400) as to whether the detec...
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WO/2007/063965A1 |
A multi-phase oscillator includes: a plurality of ring oscillators (21) each having a plurality of output ports and each formed by an odd number of inverters (20) connected in a ring; shape; and a plurality of resistance elements (30) fo...
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WO/2007/065040A2 |
An improved comparator circuit and associated methods are disclosed. In one embodiment, the comparator circuit comprises two voltage-to-time converter circuits, one for each input voltage to be compared, and an arbiter circuit for receiv...
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WO/2007/063655A1 |
There is provided a program circuit that can reduce the impoverishment of a switching element using the oxidation-reduction reaction of an electrolytic material. A voltage source (106) applies a voltage to a switching element (100). A me...
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WO/2007/060868A1 |
The number of blocks that can be stopped upon executing a target process in a programmable logic circuit portion is obtained, and the stop rate of each of a plurality of logic blocks included in the programmable logic circuit portion is ...
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WO/2007/059392A2 |
Transmit-side active signal management circuitry applies active signal management processes to a digital signal at a transmit side of an interconnect. At the receive side of the interconnect, receive-side active signal management circuit...
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WO/2007/058011A1 |
A first to a fourth sampling switch (1a to 1d), a first to a fourth sampling capacitor (4 to 7), and a first and a second charge redistribution switch (2a, 2b) are provided on the input side of a differential amplifier (8). A first and a...
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WO/2007/053425A1 |
A complex band-pass filter includes a band-pass filter (110) coupled to a voltage source (112). The band-pass filter includes a first plurality of transconductors (204) that receives a first voltage (VFC), where the first voltage control...
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WO/2007/049179A2 |
A comparator comprises a differential amplifier (T1 , T2, T8, T9) having differential inputs (IN1 , IN2) forming the comparator inputs, and a first and a second amplifier output (f1 , f2) forming the comparator outputs of a first compara...
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WO/2007/049365A1 |
Provided is a clock generating apparatus for generating a single phase clock to which a jitter is applied. The clock generating apparatus is provided with a multiphase clock generating section which generates a plurality of clock signals...
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WO/2007/049490A1 |
There is provided a method for replacing a delay amount measurement. The method obtains an initially set value of a counter can reduce the time required for calibration of a delay circuit. One of counter setting values is loaded and a de...
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WO/2007/048014A2 |
A system for and method of reducing power consumed by an electronic system is disclosed. The system includes an energy controller for controlling power to one or more functional modules or regions on the electronic system. Each of the fu...
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WO/2007/046268A1 |
A semiconductor device has a signal transmission wiring suitable for transmitting a high-frequency signal and can adjust the characteristics of the signal transmission wiring. The semiconductor device comprises a signal transmission wiri...
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