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WO/2011/041060A2 |
Described are integrated-circuit delay lines that include regulated and unregulated delay elements connected in series. The regulated delay elements exhibit relatively long delays that are stable over process, voltage, and temperature. T...
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WO/2011/036516A1 |
The invention relates to a duty cycle corrector (10) for generating from an input clock signal an output clock signal having a desired duty cycle. The duty cycle corrector comprises a pulse generating stage (52, 54, 56) for generating fr...
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WO/2011/034861A1 |
A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a "delay time", thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of th...
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WO/2011/028348A2 |
Embodiments are described that compensate for a difference in a characteristic (e.g., of performance or operation) of a semiconductor device that is a function of the location of a die in a device. In one embodiment, a clock circuit may ...
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WO/2011/027489A1 |
A comparison unit compares an expected value with a count result at an end of a monitoring period of a counter for counting the number of pulses of a system clock for each monitoring period. If the comparison result shows a mismatch betw...
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WO/2011/027553A1 |
An aging diagnostic device has a reference-use ring oscillator (101) constituted by a ring oscillator using a odd-numbered plurality of logic gates constituted using CMOS circuits; a test-use ring oscillator (102) constituted by a ring o...
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WO/2011/027465A1 |
Provided is a switched capacitor circuit including: two or more internal capacitances, one or more amplifiers, and two or more internal switches. The switched capacitor circuit further includes: a sampling capacitance arranged at the ne...
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WO/2011/025360A1 |
The present invention relates to a clock generator circuit (300) that is programmable and capable of self-generating two-phase non-overlapping clock signals for switch capacitor circuit applications. This clock generator circuit (300) ha...
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WO/2011/024212A1 |
A first mixer (21) generates a first clock signal and a second clock signal having a phase opposite to that of the first clock signal according to a first control signal. A second mixer (22) generates a third clock signal having a phase ...
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WO/2011/021357A1 |
Difference of a constant delay between a rising edge and a falling edge of a data signal can be reduced. A data reception circuit comprises an amplification circuit which amplifies and outputs a data signal which transmits data, a first ...
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WO/2011/016266A1 |
Disclosed is a pulse-modulated high-frequency power control method comprised of an output amplitude control process for controlling the amplitude of a pulse output and a duty control process for controlling the duty ratio of a pulse outp...
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WO/2011/013270A1 |
A monitor circuit (100) comprises a delay circuit (102) configured to have a tree structure by a plurality of elements and interconnects, a data supply circuit (101) which supplies a determining signal to the delay circuit (102), and a d...
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WO/2011/008356A2 |
A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A ...
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WO/2011/006046A1 |
The invention relates to the field of modulation and demodulation circuits, such as envelope detectors used to demodulate amplitude- modulated (AM) signals and amplitude-shift-keying (ASK) signals. By judiciously coupling an analog circu...
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WO/2011/004532A1 |
Provided is a pipeline circuit capable of flexibly controlling clock frequencies regardless of whether a pipeline operation by a flow control is stopped or not, without significantly increasing a processing latency even if a clock freque...
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WO/2011/002911A1 |
A method and circuit for attenuating positive feedback in a comparator in one embodiment includes an amplifier (102) configured to compare a first input signal (104) with a second input signal (106) and to provide an output (108) based u...
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WO/2010/150303A1 |
Provided is a timing generator for outputting a timing signal obtained by delaying input signal, which comprises a first period delay section and a second period delay section for outputting rate signals obtained by delaying the input si...
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WO/2010/146843A1 |
Disclosed is a flip-flop, provided with a plurality of latch circuits with differing resistance to soft errors, and a clock distribution unit which feeds a clock to the plurality of latch circuits, wherein the plurality of latch circuits...
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WO/2010/142204A1 |
The invention provides a clock detection method and device, which are used for resolving that current clock detection methods occupy high resources. The method comprises the following steps: a programmable device carries out frequency di...
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WO/2010/134065A1 |
In a method and circuit for recovering a sync signal from an input sync signal passing through a cable to a display device, an average value of the input sync signal is obtained during a predetermined time period so as to obtain a sync t...
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WO/2010/128637A1 |
An adder (107) is provided with N-type MOS transistors (201 to 204) and P-type MOS transistors (205, 206). The drains of the transistors (201, 203) are connected to the drain of the transistor (205). The drains of the transistors (202, 2...
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WO/2010/129824A1 |
All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block (210) is provided for computing the product of a selected duty cycle (C) and a discrete ratio (L) between a ...
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WO/2010/124558A1 |
Disclosed are a peak-avoidance regulation method and device. The device comprises a control unit and at least two output units. The control unit is used, once PWM signals are received, for controlling various output units to start to out...
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WO/2010/113213A1 |
An inverting circuit inverts an adjustment pattern signal that is input as received data. A clock adjustment control circuit acquires: a first adjusted tap value obtained in the case where a phase adjustment operation is executed in resp...
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WO/2010/112969A1 |
A circuit comprises a clock tree (714) for distributing a clock signal. A first counter (718) is arranged at a first point (724) in the clock tree. Upon detecting a triggering edge in the clock signal, the first counter sets a first curr...
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WO/2010/107706A1 |
A phase shift generation circuit has an edge detector, which receives an input pulse signal and outputs a first and a second edge signal denoting the time of occurrence of the first and second edges of the input pulse signal. The circuit...
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WO/2010/108037A1 |
A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a ...
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WO/2010/103614A1 |
Disclosed is a delay line for a differential signal wherein signal degradation and generation of common mode noise can be controlled by making a proper skew correction including delay time difference. First and second delay line elements...
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WO/2010/102382A1 |
An apparatus is provided for generating a timing signal having an input for receiving a first signal indicating successive time intervals, means for receiving a second signal indicating successive time intervals, and a generator adapted ...
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WO/2010/103576A1 |
A data reception circuit includes an automatic switching circuit which outputs such a switching signal that a first selector and a second selector select fixed pattern data and a reference clock upon a signal breakdown or a lock loss sta...
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WO/2010/104164A1 |
A first equidistant-clock signal group is used to sample a second clock signal, thereby generating a first phase difference signal. The second clock signal is delayed by equal intervals, thereby generating a second clock signal group, wh...
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WO/2010/100693A1 |
A semiconductor integrated circuit provided with a p-MOS transistor (MP11) and at least two n-MOS transistors (MN11, MN12), which are connected in series between a first power source (VDD) and a second power source (grounded power source...
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WO/2010/095095A2 |
A shrinking-pulse digital delay line has a cascade of a plurality of stages for modifying a width of a pulse propagating down the cascade. Each specific one of the stages has an input, an output and a main path between the input and the ...
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WO/2010/096069A1 |
A signal generator for use in producing a video top-of-frame signal based upon an input video signal with an input video frame including one or more input video fields and having an input video frame rate for an output video signal with ...
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WO/2010/095378A1 |
An output device outputting an output signal in response to an input signal, provided with: a plurality of drivers, each outputting an intermediate signal of a waveform corresponding to the input signal; an adding unit adding the interme...
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WO/2010/089983A1 |
Disclosed is a multi-hysteresis voltage controlled current source system that has diverse multi-hysteresis characteristics. A multi-hysteresis voltage controlled current source system is configured with binary hysteresis voltage controll...
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WO/2010/086052A1 |
An apparatus, method and computer program, the apparatus comprising: communication circuitry configured to drive, on a first occasion, a first transition of a first electrical parameter on an electrical interface to another apparatus; de...
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WO/2010/087817A1 |
An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay v...
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WO/2010/084029A1 |
The invention relates to a circuit for generating square wave pulses as transmission signals for a communication line, generating square wave pulses with good flanks and good electromagnetic compatibility. Said circuit comprises: a first...
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WO/2010/082957A1 |
A programmable-current transmit continuous-time filter (TX-CTF) system can be included in a radio frequency (RF) transmitter. The input of the TX-CTF can receive a baseband transmission signal, and the output of the TX-CTF can be provide...
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WO/2010/082239A1 |
A current lowering factor detection unit (2a) detects lowering of a power source voltage (VDD) of a dynamic comparator (1). Upon detection of lowering of the power source voltage (VDD) by the current lowering factor detection unit (2a),...
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WO/2010/077426A1 |
Methods for determining timestamps for signal timing edges for use in, e.g., a reciprocal counter for determining the frequency of a signal is disclosed, comprising the steps of inputting the signal into a tapped delay line, producing a ...
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WO/2010/076086A1 |
A clock signal duty cycle adjustment circuit includes a duty cycle correction circuit that receives a clock input signal that may need duty cycle correction. The duty cycle correction circuit may derive first and second differential cloc...
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WO/2010/076667A1 |
In a first circuit (402) for detecting clock glitches in a clock signal (400), a master counter (412) is clocked by the clock signal and memorizes a master count NM. An incrementer (428) advances the master count by one increment. A slav...
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WO/2010/073489A1 |
Disclosed is a switch device that switches the connection state between two terminals, wherein the switch device is equipped with: a switch that switches the connection state between two terminals according to a supplied control voltage;...
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WO/2010/073458A1 |
A delay setting data generation unit (10) generates delay setting data DDS in accordance with rate data DRATE. A variable delay circuit (30) delays test pattern data DPAT by a delay time τ based on the delay setting data DDS with respe...
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WO/2010/071063A1 |
The first objective is to provide a semiconductor integrated circuit capable of reducing hardware overhead and temporal overhead for the purpose of error detection, and to enable the identification of a logical element which has generate...
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WO/2010/067495A1 |
A mode determining circuit determines existence/absence of an electric system state change which causes a frequency change of a system control clock, and a clock switching circuit switches the system control clock from a system clock to ...
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WO/2010/064338A1 |
The operating speed is improved while increases in the power consumption are suppressed. A comparator is comprised of a comparison unit which outputs the comparison result of one voltage of the input differential signal and the other vol...
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WO/2010/053697A2 |
A control system includes a zero crossing detecting circuit for detecting a zero crossing of an AC signal. The circuit includes a transformer having a primary portion and a secondary portion. The primary portion receives the AC signal. T...
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