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WO/2010/050293A1 |
In an A/D converter circuit having a chopper comparator, only a small number of elements are additionally provided to impart a hysteresis characteristic to the comparator, thereby reducing the conversion errors caused by noise. In a suc...
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WO/2010/050097A1 |
Provided is a clock division circuit which generates a clock signal enabling execution or a correct communication expected in the communication with a circuit operating at a different frequency clock. The clock division circuits (10a, b...
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WO/2010/050515A1 |
Provided are a comparator and an A/D converter having the comparator which can eliminate the problem of a timing shift between two clock signals of different polarities existing in a conventional comparator and enables a low-power operat...
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WO/2010/050294A1 |
In an A/D converter circuit having a chopper-type comparator circuit, a low power consumption and low noise can be achieved in a case of a high power supply voltage, while the characteristic degradation due to a degradation of current pe...
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WO/2010/050098A1 |
A clock division circuit (11) masks (S – N) clock pulses among S clock pulses of an input clock signal according to a division ratio defined by an N/S and generates an output clock signal obtained by N/S-dividing the input clock signal...
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WO/2010/048226A1 |
An iterative method for generating a series of output signal values from a series of input signal values is described. Iterations of the method comprise the steps of obtaining a current input signal value for the current iteration, compa...
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WO/2010/043492A1 |
A method for estimating parameters of a system for spreading the spectrum of a first periodic signal according to a modulation period. An embodiment comprises the steps of sampling the first signal by means of a second periodic signal, o...
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WO/2010/044012A1 |
The present invention relates to a low-voltage self-calibrated peak detector (100). Using a two-step calibration process that compensates the offset errors introduced by the respective first, second and third comparators (122, 128, 130),...
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WO/2010/041163A2 |
A circuit arrangement is described comprising a first receiver configured to receive a first input signal, a second receiver configured to receive a second input signal, a first signal generator configured to generate a first pulse signa...
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WO/2010/041606A1 |
Provided are a hysteresis comparator and a noise generator which can significantly reduce the circuit size. Provided is also a probability resonator using the hysteresis comparator and the noise generator. When the voltage (Vs) at the ...
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WO/2010/035309A1 |
A sub delay element (14) has the same configuration as a main delay element (10) and gives a delay (τ) corresponding to a bias voltage (Vbias) to a selection clock signal (CLK1) outputted from a first selector (12). A phase detector (18...
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WO/2010/032830A1 |
A digital phase comparator of high resolution is provided without increasing the circuit area and the power consumption. A delay circuit array (21_1 to 21_n–1) generates delayed signals (CKC(1) to CKC(n–1)) obtained by delaying an i...
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WO/2010/029098A1 |
A level shifter (21) comprises a first stage (22) and a second stage (23). The first stage (22) comprises first and second inputs (34, 35) and is configured to generate a first signal (37) which indicates in a first state if either at le...
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WO/2010/029486A1 |
An electronic circuit (1) comprises an input stage (2) and a driver stage (3). The input stage (2) comprises first, second, third and fourth inputs (In1-In4), and is configured to generate a first intermediate signal (Int1) which is the ...
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WO/2010/025564A1 |
A method and system for fractionally converting sample rates. Fractional rate conversion for a transmit path of a transceiver is achieved by upsampling an input signal having a first sample rate by a first integer factor, removing aliasi...
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WO/2010/026616A1 |
Timing setting data (T1-Tn) include an arbitrary combination of set timing signals (S), which are indicative of the timings of positive edges, and reset timing signals (R) which are indicative of the timings of negative edges. A sorting ...
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WO/2010/026642A1 |
A test device for testing a device to be tested which comprises a phase comparison unit which compares the phase of the internal clock generated in the test device with a phase of a clock superimposed on a device signal outputted by the ...
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WO/2010/026902A1 |
A semiconductor integrated circuit device comprises an oscillation circuit for performing oscillation to output an oscillation signal and, when detecting that the oscillation is stopped, outputting an oscillation stop detection signal to...
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WO/2010/023509A1 |
A signal shaper (10) generates an output signal (16) representing a binary sequence, the output signal (16) being the time-dependence of a signal value F. The signal shaper is input a first signal value F0 and a different second signal v...
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WO/2010/017625A1 |
A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of ...
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WO/2010/017643A1 |
There is described a method and corresponding pulse generating device, for generating an output pulse signal having an output pulse duration. The method comprises: receiving at an input port an input pulse signal comprising an input puls...
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WO/2010/016301A1 |
A phase comparator which allows solution of the problem that a phase difference cannot be discriminated, while suppressing increase in power consumption and a circuit area. A variable delay circuit (3) adjusts the phase of a signal (φ2)...
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WO/2010/015787A1 |
This matrix of electronic cells distributed in columns of cells linked to an input of at least one monitoring signal, is characterized in that it exhibits a single input point (17) for said at least one monitoring signal (S) and in that ...
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WO/2010/013097A1 |
A buffer apparatus (164) for a communications bus comprises a driver circuit (236) having an output (208). An amplifier circuit (212) having an input (210) is coupled to the output (208) of the driver circuit (236). The driver circuit (2...
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WO/2010/013508A1 |
An inverter (15) is constituted using double gate TFTs (11, 12), and an inverter (16) is constituted using double gate TFTs (13, 14). Top gate terminals of the TFTs constituting the inverter (15) are connected to an input terminal (DAT) ...
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WO/2010/011408A1 |
This invention relates to a pulse generator circuit for delivering a short high current pulse to a load. This pulse generator comprises a junction recovery diode, a switch, a first resonant circuit and a second resonant circuit. The diod...
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WO/2010/007654A1 |
Provided is a signal output circuit which is a signal output circuit for outputting a signal and which comprises an output circuit the property of an output signal of which is varied according to the variation of a given power voltage an...
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WO/2010/006224A1 |
A device for current detection is disclosed and includes a protection circuit having a current input provided via a positive input and a negative input arranged in parallel to the positive input, a pair of diodes communicatively coupling...
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WO/2010/004747A1 |
Provided is a divider circuit for a multi-phase clock signal which can assure a sufficient data latch time even for a multi-phase clock signal having a high frequency. For example, the divider circuit includes: a main latch circuit (10)...
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WO/2010/006092A1 |
A device and method for current detecting and discriminating is disclosed. The device includes a differential receiver configured to receive a current input, a positive-side Schmitt trigger in communication with the input stage, wherein ...
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WO/2010/004684A1 |
Provided is a semiconductor integrated circuit which can reliably detect the oscillation stop of an oscillator-type oscillation circuit and reliably restart the operation of the oscillation circuit when an oscillation stop was detected. ...
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WO/2010/001456A1 |
To an input section (110), a voltage to be applied to a load (101) is input. A first resistor (120) is connected in series between the input section (110) and a supply section (150). A second resistor (130) is connected to the input sect...
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WO/2009/156580A1 |
There is provided an apparatus (300) for measuring a distance to a target (312), comprising: a transmitter (302) configured to transmit an optical pulse (310) towards the target (312), a receiver channel (304) configured to receive the o...
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WO/2009/157492A1 |
A differential transmission circuit comprises a sending unit that generates a pair of differential signals from an input signal, and sends the differential signals; a receiver that receives the differential signals sent by the sending un...
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WO/2009/156795A1 |
A semiconductor device (200) comprising timer logic (210) for generating a first modulated waveform signal, and delay logic (220), operably coupled to the timer logic (210) and arranged to provide a first delay in a rising edge of the fi...
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WO/2009/155712A1 |
A digital pulse shaping module for controlling a pulsed laser oscillator according to a digital input waveform is provided. The pulse shaping module includes a clock generator generating a plurality of phase-related clock signals and a s...
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WO/2009/154906A2 |
An apparatus and method for multi -phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals (A, B) delayed from first edges of a clock signal (CLK) having a ...
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WO/2009/149582A1 |
System and method for muting an output terminal of an electronic device. In one embodiment, the process for can include receiving one or more signals received by the controller over the first terminal, detecting a mute control signal fro...
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WO/2009/147770A1 |
A clock signal amplifier circuit comprises an inverter (11), a coupling capacitance (13) connected to the input of the inverter, two resistors (15) which are connected in series between a power supply potential and a ground potential and...
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WO/2009/144642A2 |
The present invention relates to a circuit arrangement (300) for generating non-overlapping and immune-to-1/f-noise signals as has been described. A break-before- make (BBM) circuit ensures that the differential I/Q signals (LO_0, LO_90,...
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WO/2009/140656A2 |
[A high-speed low-power latch includes three sets of transistors. A first set of transistors selects a tracking mode or a holding mode for the latch based on a clock signal having non-rail-to-rail or rail-to-rail voltage swing. A second ...
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WO/2009/133658A1 |
Provided is a multiple signal switching circuit using four input signals (IN1 to IN4), wherein a 4-input latch circuit (3b) is disposed. The 4-input latch circuit (3b), when one of the four input signals (IN1 to IN4) is a logical “L”...
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WO/2009/135228A2 |
The present invention relates to circuits and methods for detecting transistor operation in the triode region including a circuit for a transistor in a constant current source. The circuit comprises a detector having a first input, a sec...
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WO/2009/125580A1 |
Provided is a loop type clock adjustment circuit including: a variable delay circuit which applies a variable delay based on an analog signal to a reference clock so as to generate a delay clock; a phase detection unit which detects a ph...
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WO/2009/122352A2 |
A glitch monitor 20 includes a first input 22 for connecting to a circuit node 12 of a device under test 10. The input signal is fed to a plurality of test paths 26,28,30 each with an amplifier 32,34,36 arranged to compare the voltage on...
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WO/2009/118351A1 |
The invention relates to an electronic motor vehicle control system having at least one valve actuating circuit (2a, 2b) which controls a load current by means of pulse width modulation, and having at least one electronic current measuri...
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WO/2009/115979A1 |
Input/Output (I/O) pin circuits, devices, methods and systems are implemented in various fashions. According to one such method, a valid signal level is provided for a pin of an integrated circuit (IC) die. Responsive to a reset signal, ...
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WO/2009/115978A1 |
A variety of edge-detection related devices, methods and systems are implemented in various fashions. One implementation is directed to an edge detector circuit (100) for detecting an edge of an input signal and producing an output level...
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WO/2009/113657A1 |
Provided is an oscillator using a high-frequency crystal oscillator element which satisfies the excitation level required for the crystal oscillator element and can widen the variable frequency range. A limiter circuit (LM1), which has i...
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WO/2009/110172A1 |
A variable delay circuit (101) generates a plurality of delay signals (D(1), D(2), …, D(n)). An output holding circuit (102) takes in the delay signals (D(1), D(2), …, D(n)) in synchronization with the transition of a reference signa...
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