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Patent Searching and Data


Matches 101 - 150 out of 39,132

Document Document Title
WO/2019/023906A1
Provided by the embodiments of the present invention are a synchronization method, device and system, the method comprising: an unmanned aerial vehicle obtaining first time information from a satellite by means of a clock synchronization...  
WO/2019/027099A1
The present invention relates to a synchronization error compensation system and a synchronization error compensation method thereof, which are capable of estimating and compensating a synchronization error between a master and slaves su...  
WO/2019/023433A1
Timing recovery systems and methods can include receiving a signal with Nyquist shaped pulses, sampling the signal using an analog-to-digital converter at a sampling rate, generating a plurality of delayed sampled signals from the receiv...  
WO/2019/022794A1
A system and method for the synchronization of a central controller wirelessly for determining values of electrical parameters. The method includes sampling an electrical signal via at least one self-powered power sensor (SPPS); estimati...  
WO/2019/022808A1
A system and method for the synchronization of a central controller wirelessly connected to at least one self-powered power sensor (SPPS). The method includes: sampling an electrical signal by at least one SPPS; estimating by the at leas...  
WO/2019/018798A1
In accordance with aspects of the present invention, a method of synchronizing two integrated circuits is presented. A method of synchronizing two integrated circuits can include sending a first pulse from a master IC to a slave IC over ...  
WO/2019/018081A1
An apparatus is provided which comprises: a first circuitry to track a spread spectrum of a differential signal according to sampled data; and a second circuitry to adjust phase of a clock according to the spread spectrum, wherein the cl...  
WO/2018/222344A3
Aspects of the disclosure are directed to determining an offset calibration step size of a sample latch. In accordance with one aspect, the disclosure relate to a Decision Feedback Equalizer (DFE) input section including a E sample latch...  
WO/2019/009060A1
This disclosure relates to a transmission device and method, and a reception device and method, which make it possible to suppress an increase in power consumption. Data in which a clock signal is embedded is transmitted, and the frequen...  
WO/2019/006715A1
The present invention provides a distributed secure beamforming method and apparatus based on feedback control. The method comprises: receiving feedback signals sent by a receiving end device, the feedback signals being used for indicati...  
WO/2019/003320A1
A grand master device (GM) (10) and a slave device (S1) (20) are connected to each other via a general-purpose hub (HUB) (30) the relay delay of which is not constant. The grand master device (GM) (10) acquires a current time, as the tra...  
WO/2019/004867A1
The invention relates to the field of means for converting discrete (digital) information, including communication and location in various environments, telemetry, recording/reading information, radio, television, and other uses. The tec...  
WO/2019/000205A1
Provided in the embodiments of the present invention are a method and system for timing synchronization of an unmanned aerial vehicle and an unmanned aerial vehicle, the method comprising: a communication system of an unmanned aerial veh...  
WO/2019/003493A1
The clock recovery system (10) is provided with: a sampler part (11) for sampling received data using 2N phase clocks and outputting 2N x M sampling signals; a data selection part (102) for selectively outputting n x M restoration signal...  
WO/2019/003950A1
The present technology relates to a wireless terminal, an information processing device, an information processing method, and a program which enable time synchronization with high accuracy even when the number of acquirable satellites i...  
WO/2019/002911A1
A variable delay interface configured to introduce a controllable, variable delay between a radio equipment controller and a radio equipment is provided. The interface includes a variable rate change filter, VRCF, having a signal input, ...  
WO/2019/005875A1
A gear-shifting serializer-deserializer (SerDes) is provided that uses a first divisor value to form a divided clock while de-serializing a serial data stream prior to a lock detection and that uses a second divisor value to form the div...  
WO/2018/235259A1
An image transfer system having an imaging terminal that transmits imaged image data according to an imaging period, and a display terminal that receives the imaged image data and displays the same according to a display period, said ima...  
WO/2018/233450A1
The present application provides a time conversion method and device, an apparatus, a storage medium, and a processor. The time conversion method comprises: obtaining time difference information between a local end and a peer end; receiv...  
WO/2018/235258A1
An image transfer system having an imaging terminal that transmits imaged image data according to the period of an imaging timing, and a display terminal that receives the imaged image data and displays the same according to the period o...  
WO/2018/227856A1
Provided are a method and device for transmitting synchronization signal blocks. The method comprises: determining M target frequency domain positions, in a bandwidth component carrier, for bearing M synchronization signal blocks, wherei...  
WO/2018/225190A1
User equipment comprises: a reception unit that receives a first primary synchronization signal used in a first cell and a second primary synchronization signal used in a second cell; a first correlation detection unit that estimates the...  
WO/2018/219271A1
Disclosed are a synchronous network alarming method and apparatus. The synchronous network alarming method comprises: obtaining quality level information of a tracked synchronization source; and if the synchronization quality level of th...  
WO/2018/222344A2
Aspects of the disclosure are directed to determining an offset calibration step size of a sample latch. In accordance with one aspect, the disclosure relate to a Decision Feedback Equalizer (DFE) input section including a E sample latch...  
WO/2018/220743A1
Provided is a communication device for an elevator with which it is possible to perform, using a simple configuration, a highly reliable correction on the time managed by a control panel of the elevator. The communication device is provi...  
WO/2018/218342A1
A system and method enables loosely-coupled lock-step computing including sensors that detect or measure a physical property and server groups. Each server group is serially linked to another server group and includes server instances op...  
WO/2018/221238A1
The present invention efficiently notifies a counterpart device whether a clock to be synchronized with said counterpart device has been correctly synchronized. This wireless device is provided with: a main control unit; a wireless contr...  
WO/2018/204462A3
System and method of timing recovery using calibration logic to correct non-idealities related to phase interpolation. The calibration logic includes a Look-Up Table (LUT) preloaded with a set of expected output phases of the phase inter...  
WO/2018/214856A1
Disclosed are a method and device for data processing. The method may comprise: shifting output data in a current SERDES output clock cycle into a cache of a pre-set length; determining a reference position in current cache data accordin...  
WO/2018/214138A1
The present application provides a method, a device, a transmitter, and a receiver for detecting syncwords. After inserting syncwords in a data frame to be transmitted, a transmitter transmits the data frame to be transmitted inserted wi...  
WO/2018/217783A1
Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal fro...  
WO/2018/214606A1
Disclosed are a clock process method and apparatus, and a PTP device. The clock process method in the embodiments of the present disclosure comprises: calculating a time deviation according to an extracted timestamp; correcting, by means...  
WO/2018/167145A3
Exemplary embodiments provide a data transmitter for transmitting data to a data receiver, individual communication information being known to the data transmitter and data receiver. The data transmitter is designed to generate an indivi...  
WO/2018/211761A1
An on-board communication device mounted in a vehicle, wherein the on-board communication device is provided with: a storage unit for storing a first encryption time, which is the time required to encrypt data in another on-board communi...  
WO/2018/209314A1
Systems and methods for synchronizing the clocks of a central device and one or more destination devices are disclosed. In some embodiments the central device and destination devices are implemented in a space-based or high-altitude asse...  
WO/2018/202038A1
Disclosed in the present invention are an uplink synchronization timing deviation determination method and device, for solving the problem in the prior art that a base station in an NB-IoT system has low accuracy in determining an uplink...  
WO/2018/204462A2
System and method of timing recovery using calibration logic to correct non-idealities related to phase interpolation. The calibration logic includes a Look-Up Table (LUT) preloaded with a set of expected output phases of the phase inter...  
WO/2018/204010A1
An apparatus is provided which comprises: a data slicer to receive first data sampled by a data clock; an edge slicer to receive second data sampled by an edge clock; and a Least Mean Square (LMS) circuitry coupled to the data and edge s...  
WO/2018/204459A1
System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel ch...  
WO/2018/196600A1
Provided are a method and device for configuring a link group. The method comprises: a first device acquiring first state information about M links between a source end device and a receiving end device, where the first state information...  
WO/2018/197011A1
A method of frame synchronization comprises receiving a stream of bits, the stream comprising a sequence of frames, wherein each frame comprises a frame counter value representing the number of the frame in the sequence, and frame check ...  
WO/2018/196223A1
The embodiments of the present invention disclose a data processing method and a relevant device for improving the accuracy of a system time difference between time systems in a time synchronization system. The method in the embodiments ...  
WO/2018/200373A1
A device may include an input for receiving information communicated from a host to the device and a controller configured to recover a device reference clock on the device, the device reference clock proportional to a host reference clo...  
WO/2018/187018A1
A source device and a sink device may be connected using an interface cable comprising at least first and second physical channels. The first physical channel may be used to transmit video data unidirectionally from the source device to ...  
WO/2018/185121A1
The invention relates to a method for forming a digital value from a clock signal (101) and from a digital data signal (102), wherein the clock signal (101) is scanned in order to obtain a clock signal digital value sequence, wherein the...  
WO/2018/179920A1
[Problem] To control delay time with high accuracy. [Solution] A delayed locked loop circuit provided with: a first delay circuit that comprises at least one first delay device and at least one second delay device, the first delay device...  
WO/2018/182662A1
An apparatus for interpolating between a first and a second signal is provided. The apparatus includes a plurality of interpolation cells coupled to a common node of the apparatus. Further, the apparatus includes a control circuit config...  
WO/2018/179165A1
A motion controller (1) according to the present invention is provided with a calculation unit (11) that generates a position command for each calculation period, which is shorter than a communication period in synchronous communication,...  
WO/2018/182907A1
Examples provide a modulation circuit and apparatus, a demodulation circuit and apparatus, a transmitter, a receiver, a system, a radio frequency circuit, a mobile terminal, and methods and computer programs for modulating and demodulati...  
WO/2018/179066A1
[Problem] To provide a broadcast wave synchronization signal converting device that synchronizes broadcast waves with GNSS signals on a reception side and corrects the broadcast waves to global standard times by use of correction values,...  

Matches 101 - 150 out of 39,132