CMOS INTEGRATED CIRCUIT

Japanese Patent JPS607169

A

PURPOSE: To prevent latch up, by providing a specified parasitic thyristor, whose breakover voltage is lower than that of other thyristors and whose holding voltage is higher than a power source voltage.

CONSTITUTION: In a plurality of parasitic thyristors accompanied by a CMOS integrated circuit, the breakover voltage of the specified parasitic thyristor, e.g., the thyristor accompanied by input and output circuits, is made lower than that of the other thyristors and its holding voltage is made higher than a power source voltage. In this way, the thyristor is operated against external noises in an overwhelming mode, the external noises are removed, and latch up does not occur. In order to reduce the breakover voltage smaller than the voltage in an inner circuit, a junction, at which guard rings 25 and 26 are contacted, is formed so that the breakdown voltage between a well and substrate in an input output substrate becomes low. In order to make the holding voltage large, the guard rings 25 and 26 are provided, and the emitter concentration of a parasitic bipolar transistor is reduced.

JPS61187356	SEMICONDUCTOR INTEGRATED CIRCUIT
JP4368840	Manufacturing method of semiconductor devices, electronic devices with built-in semiconductor devices, and semiconductor devices
JPH0621449	SHORT CHANNEL MOS-TYPE TRANSISOR AND MANUFACTURE THEREOF

KATOU KINYA
KAMIHIRA KAZUTAKE
WADA TSUTOMU

JP11440283A

January 14, 1985

June 27, 1983

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NIPPON TELEGRAPH & TELEPHONE

H01L27/08; H01L27/092; H01L29/78; (IPC1-7): H01L27/08; H01L29/78

Toshio Takayama

Next Patent: COMPLEMENTARY TYPE SEMICONDUCTOR DEVICE