Title:
LOGIC CELL
Document Type and Number:
Japanese Patent JP3660184
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enhance the operating speed of a ripple carry adder by devising delay reduction and a circuit configuration of a three-input majority decision logic cell.
SOLUTION: The three-input majority decision logic cell is formed of four- stages of layered transistors(TRs) to reduce the cell width and a delay in a carry propagation path is reduced through transistor sizing. Furthermore, the cell function is extended to reduce a load capacity of the carry propagation path thereby conducting high speed processing.
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| JPH04316161 | MULTIINPUT ARITHMETIC CIRCUIT |
| JPH0743644 | [Title of Invention] Adder |
Inventors:
Kazuo Taki
Application Number:
JP37588999A
Publication Date:
June 15, 2005
Filing Date:
November 23, 1999
Export Citation:
Assignee:
AIL Co., Ltd.
International Classes:
G06F7/50; G06F7/501; G06F7/506; H01L21/82; H01L21/822; H01L21/8238; H01L27/04; H01L27/092; H03K19/0948; H03K19/23; (IPC1-7): H03K19/23; G06F7/50; H01L21/82; H01L21/822; H01L21/8238; H01L27/04; H01L27/092; H03K19/0948
Domestic Patent References:
| JP9200032A | ||||
| JP60080251A | ||||
| JP59127424A | ||||
| JP10335470A | ||||
| JP9045785A |
Attorney, Agent or Firm:
Yuzo Agata