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Patent Searching and Data


Title:
MOUNTING STRUCTURE FOR DRAW-OUT TERMINAL OF THICK FILM INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS5817650
Kind Code:
A
Abstract:

PURPOSE: To improve the degree of freedom of the lead-out terminals, and to miniaturize the thick film integrated circuit device by each forming a plurality of electrode terminal sections mutually connected to a thick film integrated circuit to the outer circumferential section and inside of an insulating substrate and connecting respective lead-out terminal to these electrode terminal sections and leading them out.

CONSTITUTION: The electrode terminal sections 13a, 13b, which are mutually separated and mutually connected to the thick film integrated circuit, are shaped to the inside 10b on the insulating substrate 10, and the draw-out terminals 11 are arranged so as to be led out of the inside 10b of the insulating substrate 10 by each connecting several connecting section 12a, 12b of the lead-out terminals 11 to these electrode terminal sections 13a, 13b by solder 14a, 14b. Since the lead-out terminals 11 are led out of not only the outer circumferential section 10b of the insulating substrate 10 but also the inside b while the internal elements of the thick film integrated circuit are mutually connected by the lead- out terminals 11, the degree of freedom of the lead-out terminals is improved, and the thick film integrated circuit device can be miniaturized.


Inventors:
HIRAMA TOSHIAKI
Application Number:
JP11610781A
Publication Date:
February 01, 1983
Filing Date:
July 23, 1981
Export Citation:
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Assignee:
HITACHI ELECTRONICS
International Classes:
H01L23/50; H01L23/495; H05K3/34; (IPC1-7): H01L23/48
Attorney, Agent or Firm:
Masaki Yamakawa