Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2011/013270
Kind Code:
A1
Abstract:
A monitor circuit (100) comprises a delay circuit (102) configured to have a tree structure by a plurality of elements and interconnects, a data supply circuit (101) which supplies a determining signal to the delay circuit (102), and a delay evaluation circuit (103) which is connected to the end point of a delay circuit (102) and evaluates the delay state of the determining signal. This monitor circuit (100) is used to control, based on the output of the delay evaluation circuit (103), at least one of the following: the power supply voltage of the semiconductor circuit, the board voltage, and the clock frequency. By positioning the circuits forming the monitor circuit (100) at the gaps in the semiconductor device with a layout tool, increase in circuit area can be minimized while highly precise delay monitoring can be performed.
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Inventors:
KISHISHITA KEISUKE
Application Number:
PCT/JP2010/002039
Publication Date:
February 03, 2011
Filing Date:
March 23, 2010
Export Citation:
Assignee:
PANASONIC CORP (JP)
KISHISHITA KEISUKE
KISHISHITA KEISUKE
International Classes:
H01L21/822; H01L27/04; H03K5/13
Foreign References:
| JP2009159503A | 2009-07-16 | |||
| JP2009152311A | 2009-07-09 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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