Title:
半導体ウエハの製造方法
Document Type and Number:
Japanese Patent JP6621304
Kind Code:
B2
Abstract:
In a first step, protrusions (42) are formed on a surface of an SiC substrate (40), and the SiC substrate (40) is etched. In a second step, the protrusions (42) of the SiC substrate (40) are epitaxially grown through MSE process, and an epitaxial layer (43a) containing threading screw dislocation, which has been largely grown in the vertical (c-axis) direction as a result of MSE process, is at least partially removed. In a third step, MSE process is performed again on the SiC substrate (40) after the second step, to cause epitaxial layers (43) containing no threading screw dislocation to be grown in the horizontal (a-axis) direction to be connected at the molecular level, so that one monocrystalline 4H-SiC semiconductor wafer (45) having a large area is generated throughout an Si-face or a C-face of the SiC substrate (40).
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Inventors:
Tadaaki Kaneko
Kutsuma Hotori
Akira Ashida
Kutsuma Hotori
Akira Ashida
Application Number:
JP2015220064A
Publication Date:
December 18, 2019
Filing Date:
November 10, 2015
Export Citation:
Assignee:
School corporation Kansai Gakuin
International Classes:
C30B29/36; C30B19/04; C30B19/12
Domestic Patent References:
| JP2010265126A | ||||
| JP2013043822A |
Attorney, Agent or Firm:
Naomi Katsura River