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Title:
CHIP CARRIER
Document Type and Number:
Japanese Patent JPS62217620
Kind Code:
A
Abstract:

PURPOSE: To shorten the wire interconnecting length in a chip carrier to a large extent, by forming conductor columns on connecting terminals so as to penetrate an insulating protection film.

CONSTITUTION: On one surface of an LSI chip 2, integrated electronic circuits and connecting terminals are formed. The surface for forming the electronic circuits and the connecting terminals is covered with an insulating protection film 4. At this time, conductor columns 3 are formed on the connecting terminals so as to penetrate the protection film 4. A chip carrier 1 is bonded on a substrate 5 in a face down posture as in a flip-chip mounting by using the conductor columns 3. Thus, the wiring interconnection length in the chip carrier 1 can be shortened to a large extent.


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Inventors:
NAKANO FUMIO
HONJO HIROSHI
SOGA TASAO
AMAGI SHIGEO
Application Number:
JP5921386A
Publication Date:
September 25, 1987
Filing Date:
March 19, 1986
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/60; (IPC1-7): H01L21/60
Domestic Patent References:
JPS5643748A1981-04-22
JPS6094744A1985-05-27
Attorney, Agent or Firm:
Akio Takahashi (2 outside)



 
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