Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ELEMENT LAYOUT METHOD
Document Type and Number:
Japanese Patent JP2001142934
Kind Code:
A
Abstract:

To provide a method for optimizing an element layout with a small number of times of processing in the design in the design of a semiconductor device.

Concerning a method for searching an optimal layout solution for minimizing a cost function by performing a thermally balanced state search based on Monte Carlo simulation in the layout design of the semiconductor device, a minimum change for applying the unit of a variation is defined concerning all state changes, which can be expressed on a location expression space, the average value of variations of a cost function value per the minimum change concerning one location problem is defined as a cost change characteristic value dEc of the relevant location problem, a probability to allow a location change to increase the cost function value equal with the cost change characteristic value dEc at the time of the thermally balanced state search is expressed as the function (H (t)) of a virtual temperature(t). The above thermally balanced state search is executed at the virtual temperature for applying the maximal or minimal point of an nth-order derivative (n=1, 2,..., N) provided by successively repeating the differentiation of H (t) with respect to (t) just for a prescribed number of times N.


More Like This:
Inventors:
SAIGA SHUNJI
Application Number:
JP32799199A
Publication Date:
May 25, 2001
Filing Date:
November 18, 1999
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/82; G06F17/50; G06F19/00; G06Q50/00; G06Q50/04; G06F17/00; (IPC1-7): G06F17/50; H01L21/82
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)