Title:
PHASE OFFSET CALCULATING CIRCUIT AND SIGNAL POINT MAPPING CIRCUIT
Document Type and Number:
Japanese Patent JP3772089
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To perform a low power consumption by reducing a scale of a circuit when an amplitude and a phase of a transmission signal are controlled to realize a transmission diversity.
SOLUTION: When signals of I and Q of QPSK modulation signals are mapped on a phase flat surface, first sign (+ and -) is converted by a sign converter 60, and phase offset of magnification of 90° is realized. Then, the amplitude is regulated by an amplitude regulator 61. Then, offset smaller than 90° (e.g. fixed 45° offset) is realized by a phase offset arithmetic unit 62. Since the phase offset of magnification of 90° is realized by the sign conversion at a stage of the original data, a circuit constitution can be very simplified. The phase offset smaller than 90° can be easily realized, and a circuit simplification and the low power consumption can be performed.
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Inventors:
Kazumasa Ohashi
Application Number:
JP2000383781A
Publication Date:
May 10, 2006
Filing Date:
December 18, 2000
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H04L27/20; H04B1/707; H04B7/06; H04J13/00; H04L27/04; (IPC1-7): H04B1/707; H04L27/20
Domestic Patent References:
| JP11027156A | ||||
| JP9153883A | ||||
| JP6232918A |
Foreign References:
| WO2000072465A1 |
Attorney, Agent or Firm:
Koichi Washida
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