Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS58103149
Kind Code:
A
Abstract:
PURPOSE:To enhance the degree of integration per occupying area and yield at manufacturing time of the semiconductor device by a method wherein wirings between elements of semiconductor circuit dispersed three-dimentionally, arranged laminatedly and divided into multilayers are provided at the side of the laminate. CONSTITUTION:Chips 1, 2 of two sheets are laminated as to make the respective semiconductor circuit formed face sides to face each other, and are fixed with a proper organic adhesive of epoxy resin, urethane resin, phenol resin, etc. The wirings 51, 52, 53 are arranged respectively between pads of three groups of fellow VDD's of the chips 1, 2, fellow VSS's of the chips 1, 2, and the OUT1 of the chip 1 and the IN2 of the chip 2, and the semiconductor integrated circuit 6 of MOS inverter two stage connection is formed in the laminate 4 by the wirings thereof. Pads 61, 62 consisting of aluminum, etc., and necessary for input/output, etc., to the semiconductor integrated circuit thereof are provided to the IN1 and the OUT2 on the pads exposing side face of the laminate 4.
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Inventors:
TERASAWA TOMIZOU
TOMONARI SHIGEAKI
TOMONARI SHIGEAKI
Application Number:
JP20287981A
Publication Date:
June 20, 1983
Filing Date:
December 15, 1981
Export Citation:
Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
H01L27/00; H01L21/60; H01L25/065; (IPC1-7): H01L21/60; H01L27/12
Attorney, Agent or Firm:
Takehiko Matsumoto