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Patent Searching and Data

Document Type and Number:
Japanese Patent JP2000040384
Kind Code:

To provide a sense amplifier which can read out data from a memory transistor at high speed and stably.

A sense amplifier 10 is constituted of a load transistor 4 provided on a bit line BL of a memory transistor 2, a differential amplifier AMP, and a comparator COM. The differential amplifier AMP controls the load transistor 4 so that drain voltage of the memory transistor 2 is made equal to a first reference voltage Vref1 inputted from the outside, the comparator COM compares an output from this differential amplifier AMP with second reference voltage Vref2, and outputs the compared result as a read-out signal of data from the memory transistor 2. In this sense amplifier 10, as it is enough that only one of the load transistor 4 is provided on the bit line BL, parasitic capacity and parasitic resistance of the bit line BL is reduced compared to conventional one and high speed read operation can be realized. Also, a noise proofing property can be improved by a constant voltage circuit consisting of the load transistor 4 and the differential amplifier AMP.

Application Number:
Publication Date:
February 08, 2000
Filing Date:
July 17, 1998
Export Citation:
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International Classes:
G11C16/06; (IPC1-7): G11C16/06
Attorney, Agent or Firm:
Adachi Tsutomu