Title:
TIMING SIGNAL GENERATION CIRCUIT
Document Type and Number:
Japanese Patent JP3183494
Kind Code:
B2
Abstract:
PURPOSE: To generate a timing signal of high resolution and high accuracy by providing m-stages of variable delay elements, which operates by synchronizing with highly accurate clock and is stable in self heat generation, to prevent timing accuracy from reduction.
CONSTITUTION: A system generating the delay time of the integral multiple of a CLK period is executed by a synchronizing delay circuit 110. In order to generate the minute delay of 1/m of the CLK period, delay time per one-step of variable delay element constituting a variable delay circuit 120 is controlled to be the delay time of 1/m of the CLK period by a feed back circuit 150. Namely the whole delay time of the variable delay elements of m-steps is equal to the period of CLK. The output of each variable delay element of this variable delay circuit 120 consisting of m-steps of variable elements becomes what is obtained by dividing CLK into m-phases equally. One CLK is selected from among the m-phases of CLKs by a selector circuit 130. This selector circuit 130 is controlled by the output of the synchronizing delay circuit 110.
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Inventors:
Toshiyuki Okayasu
Hideo Sakai
Hideo Sakai
Application Number:
JP10295595A
Publication Date:
July 09, 2001
Filing Date:
April 04, 1995
Export Citation:
Assignee:
Advantest Corporation
International Classes:
G06F1/06; H03K5/13; H03L1/00; H03L7/00; H03L7/08; (IPC1-7): H03K5/13; H03L1/00
Domestic Patent References:
| JP5199088A |
Other References:
【文献】国際公開90/329(WO,A1)
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