Title:
MEMORY
Document Type and Number:
Japanese Patent JPS59171100
Kind Code:
A
Abstract:
A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of storage elements to a plurality of data lines. Control circuitry is also provided that is connected to the array for regulating the reading and writing of data to and from the data lines to the storage elements addressed by the address lines. A pipeline circuit is also provided that is connected to the address lines and to array of storage elements to store in response to the control circuit an address contained on the address lines. This memory system architecture allows for the address to be stored to allow the second address to be placed on the address lines while the first addressed data is being accessed from the memory array. This memory system also provides for the parity to be generated for the data in the array during the access of the data for the first address or after the pipeline circuit has been loaded with the second address.
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Inventors:
JIEEMUSU ETSUCHI KURAIN
DEBITSUDO EMU CHIYASUTEIN
JIEEMUSU DEII GARIA
DEBITSUDO EMU CHIYASUTEIN
JIEEMUSU DEII GARIA
Application Number:
JP25251183A
Publication Date:
September 27, 1984
Filing Date:
December 29, 1983
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
G11C11/413; G06F12/00; G06F12/02; G06F12/14; G06F13/28; G06F21/60; G06F21/62; G06F21/79; G11C7/00; G11C7/10; (IPC1-7): G06F13/00; G11C11/34; G11C29/00
Domestic Patent References:
| JPS57135489A | 1982-08-21 |
Attorney, Agent or Firm:
Hideto Asamura