PURPOSE: To design a higher-density CMOS integrated circuit by a method wherein a P well and N well are formed opposed to each other and the two are isolated from each other with a thin isolating region positioned between the two.
CONSTITUTION: An N+ region 15 and P+ region 16 are formed in an N type Si substrate 10. A region under the N+ region 15 is surrounded by a P type well region 9. Formation by self-alignment by using the mask of the N+ region 15 eliminates the need for an additional region for masking and higher density can be realized. Next, an epitaxial layer 17 is grown. Protruding columns 18, 19 are built, to be imbedded with ions of P type and N type dopants, respectively, for the realization of the P type protruding column 18, N type protruding column 19. A field oxide film 12 is formed in the isolating region and then a gate oxide film 21 is formed. After the formation of an N+ region 151 and P+ type region 161, an interlayer insulating film 22, very likely by means of CVD. PSG, then a junction hole 24 at a desired area, finally electrodes 231∼233 very likely of Al, are formed.
| JPS62268155 | MANUFACTURE OF CMOS-FET STRUCTURE |
| JP3321899 | [Title of Invention] Semiconductor device |
| JP3968745 | ANTI-FUSE STRUCTURE AND ITS FORMING METHOD |
OOKURA OSAMU
KIMURA SHINICHIROU
