Title:
光電子デバイスを形成するためのドナー基板を製作するためのプロセス、このプロセスからもたらされる基板の集合
Document Type and Number:
Japanese Patent JP6980964
Kind Code:
B2
Abstract:
A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.
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Inventors:
Sotta, david
Application Number:
JP2019543901A
Publication Date:
December 15, 2021
Filing Date:
February 26, 2018
Export Citation:
Assignee:
Soitec
International Classes:
H01L21/20; C30B29/38; H01L21/02; H01L27/12; H01L33/32
Domestic Patent References:
| JP2010093233A | ||||
| JP2011530179A | ||||
| JP2013511834A | ||||
| JP2012514316A | ||||
| JP2009032713A |
Foreign References:
| US20150270120 |
Attorney, Agent or Firm:
Ikeda adult
Junichiro Sakamaki
Masakazu Noda
Junichiro Sakamaki
Masakazu Noda