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Patent Searching and Data


Title:
CLOCK REGENERATING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/1992/002080
Kind Code:
A1
Abstract:
A clock regenerating circuit for improving the SN ratio of a D/A converter of a PWM type, which comprises a first clock regenerating part (11) having a quartz-crystal (11a) and a voltage controlled oscillator (11b), and a second clock regenerating part (12) which generates an objective clock signal, multiplying the frequency of the output signal of the first clock regenerating part (11). The second clock regenerating part (12) comprises a phase comparator (22), a loop filter, a voltage controlled oscillator (26) of a resistance-capacitance type, and frequency demultiplier (25). Further, the loop filter comprises a second LPF (24) controlling the oscillating frequency of the voltage controlled oscillator (26) of a resistance-capacitance type, and a first filter (23) which has a cut-off frequency higher than that of the second LPF (24), and has a filter characteristic capable of cutting off the frequency components above the frequency of the output signal of the first clock regenerating part (11). Thus, unnecessary spectrum components are prevented from entering the D/A converter.

Inventors:
YAMATE KAZUNORI (JP)
DANMOTO KEIICHI (JP)
Application Number:
PCT/JP1991/000953
Publication Date:
February 06, 1992
Filing Date:
July 17, 1991
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD (JP)
International Classes:
H03L7/06; H03L7/093; H03L7/23; H03M1/82; H04B1/10; H04J3/16; (IPC1-7): H03L7/093; H03L7/18; H03M1/82
Foreign References:
JPS5819029A1983-02-03
JPS63164619A1988-07-08
JPS5736048U1982-02-25
JPS58137333A1983-08-15
JPS55153488A1980-11-29
Other References:
See also references of EP 0493607A4
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