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Patent Searching and Data


Title:
DIELECTRIC LAYER FILLING METHOD FOR STRAIGHT-HOLE THROUGH SILICON VIA
Document Type and Number:
WIPO Patent Application WO/2023/207399
Kind Code:
A1
Abstract:
The present invention relates to a dielectric layer filling method for a straight-hole through silicon via, comprising: thinning the back surface of a wafer, and manufacturing a through silicon via; forming an insulating layer on the back surface of the wafer and in the through silicon via, and removing the insulating layer at the bottom of the through silicon via; forming metal wires in the through silicon via and on the insulating layer; and forming a dielectric layer in the through silicon via and on the wafer by means of a vacuum lamination or vacuum gluing process. By means the method, a metal layer on the inner wall of a straight-hole through silicon via can be effectively protected, and the reliability of a chip is enhanced; moreover, because the through silicon via is filled with a dielectric layer, the surface of a wafer is relatively flat, and a multi-layer re-wiring structure can be easily achieved without the problem of line discontinuity.

Inventors:
CHEN LIJUN (CN)
DAI FENGWEI (CN)
SUN PENG (CN)
CAO LIQIANG (CN)
Application Number:
PCT/CN2023/081818
Publication Date:
November 02, 2023
Filing Date:
March 16, 2023
Export Citation:
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Assignee:
NAT CENTER FOR ADVANCED PACKAGING CO LTD (CN)
International Classes:
H01L21/768
Foreign References:
CN114883251A2022-08-09
CN105655320A2016-06-08
CN105489550A2016-04-13
CN103441097A2013-12-11
CN102270603A2011-12-07
CN101483149A2009-07-15
Attorney, Agent or Firm:
SHANGHAI ZHISHENG INTELLECTUAL PROPERTY OFFICE (CN)
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