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Patent Searching and Data


Title:
MEMORY AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2022/042019
Kind Code:
A1
Abstract:
Embodiments of the present application provide a memory and a manufacturing method therefor. The memory comprises: a substrate, the substrate being provided with multiple mutually separated bit lines, and the bit lines comprising bit-line conductive layers and bit-line insulating layers that are successively stacked; an insulating layer, and capacitor contact holes, the insulating layer being located on the side walls of the bit-line conductive layers and the side walls of the bit-line insulating layers, the capacitor contact holes being located between adjacent bit-line conductive layers, the insulating layer being exposed to the side walls of the capacitor contact holes, and the opening size of the capacitor contact holes gradually increasing in the direction of the substrate pointing to the insulating layer. In the embodiments of the present application, the opening size of the capacitor contact holes gradually increases in the direction of the substrate pointing to the insulating layer, such that a filling effect obtained by filling the capacitor contact holes with a conductive material is good, the electrical conductivity of capacitor contact plugs formed in the capacitor contact holes is facilitated to improve, and thus, the electrical properties of a memory structure are improved.

Inventors:
LU JINGWEN (CN)
Application Number:
PCT/CN2021/103802
Publication Date:
March 03, 2022
Filing Date:
June 30, 2021
Export Citation:
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Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/768
Foreign References:
CN106941097A2017-07-11
CN104649214A2015-05-27
CN1534362A2004-10-06
CN211017075U2020-07-14
US20050280035A12005-12-22
Attorney, Agent or Firm:
BEIJING LINKAW PATENT ATTORNEY LAW FIRM (CN)
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