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WO/2002/095972A1 |
A code division multiple-access receiver comprises an analog-to-digital converter for digitising a demodulated spread signal. The analog-to-digital converter is a Sigma-Delta modulator. The receiver also comprises a despreader comprising...
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WO/2002/091581A2 |
A photonically sampled analog-to-digital converter using parallel channels of sampling and quantizing. The parallel combination achieves cancellation of the spurs that result from the nonlinear transfer function of the samplers. The samp...
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WO/2002/091585A1 |
The invention relates to a cascade sigma-delta (SD) modulator in which different sampling frequencies are used in each of the stages of said modulator. The use of said multi-frequency cascade SD modulator optimises power consumption in t...
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WO/2002/089316A2 |
A method and system are disclosed for operating two or more integrator amplifiers with different power supplies for a modulator of an analog-to-digital ('A/D') converter. A first, upstream integrator (int1) is operated with one power sup...
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WO/2002/089333A1 |
A method and system of operating dynamic element matching ('DEM') system with two or more power supplies are disclosed. A connection system (12) of the DEM system is driven with one power supply operating at one voltage. Connection syste...
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WO/2002/084884A1 |
The invention concerns a sigma-delta modulator comprising at least a resonator (110a, 110b), a converter (120) for converting an analog signal from the resonator into a digital signal with temporal information, and a feedback loop connec...
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WO/2002/084880A2 |
The invnetion relates to a feedback A/D-converter which contains at least one analog-digital-converter (5) and at least one digital-analog-converter (8) in at least one feedback loop. Said feedback A/D converter comprises a first means f...
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WO/2002/080370A2 |
The invention relates to a method and a device for the digital transmission of analogue signals, whereby an oversampling in analogue-digital and digital-analogue converters is carried out. A digital-analogue conversion is thus carried ou...
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WO/2002/078194A2 |
A novel method and apparatus for conditioning an analog signal before it is input to a downstream device such as a delta-sigma analog-to-digital converter is disclosed. An analog conditioning circuit having a reference voltage generator ...
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WO/2002/078193A1 |
The invention relates to a noise-shaping method for a sigma-delta modulator, wherein essential energy fractions of the quantization noise are displaced to frequency ranges outside the useful band, wherein a dither signal (D(z)) is fed in...
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WO/2002/071620A1 |
While a digital input is oversampled up to eight times to process and the oversample data into a specified digital fundamental waveform with multipliers/adders (4-10) to carry out only folding operation with delay circuits 11¿-1?-11¿-4...
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WO/2002/071621A2 |
A hybrid loop filter includes an integrator having an input and an output wherein the output forms an output of the hybrid loop filter, a plurality of transconductance amplifiers having an input and an output wherein each output of the p...
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WO/2002/067522A1 |
A phase detection circuit comprises a quadrant identifying unit (101) for identifying the quadrant of a received signal on the basis of a received base band signal, a rotational projection unit (102) for projecting the received signal, a...
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WO/2002/065644A2 |
A multi-stage circuit that includes a number of stages, with at least one stage being of a first tape and at least one stage being of a second tape. Each stage receives either a circuit input signal or an output signal from a preceding s...
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WO/2002/063772A2 |
A data item with an item width of N bits is fed to a sigma-delta programmer. The highest-order L bits of the data item represent the places before the decimal point and the remaining N-L low-order bits represent the decimal places of the...
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WO/2002/063773A2 |
A multi-bit sigma-delta analog to digital converter has a quantizer, a loop filter circuit, and a digital to analog feedback circuit. The quantizer, loop filter, and digital to analog feedback circuit have a loop gain associated therewit...
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WO/2002/061947A1 |
An arrangement for runtime compensation of a runtime difference, arising through emulation of a high frequency signal, is disclosed, with a signal x(t), for emulation by means of a signal processing device, which emulates the signal x(t)...
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WO/2002/061950A2 |
The invention relates to a sigma-delta modulator for digitizing a high-frequency input signal, comprising an analog input, a digital output and a feedback branch for suppressing quantification errors. Said modulator is further characteri...
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WO/2002/056477A2 |
Gain scaling of multistage, mutli-bit delta sigma modulators for higher signal-to-noise ratios. In a multistage delta sigma modulator having a modulator stage with an integrator, a multi-bit quantizer, and a multi-bit digital-to-analog c...
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WO2000051240A9 |
A technique for correcting higher order delta sigma modulators (204, 300) in audio components, which use mutually nonlinar feedback and feed forward functions (136, 138, 140, 142, 214, 216, 218, 200, 324, 326, 328, 330, 332, 1202, 1204)....
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WO/2002/048904A1 |
An FIR decimation filter includes the a shift register (51) having M flip-flops arranged in M/R rows (52, 54, 56, 58) of R bits. Each row has a left tap and a right tap. The rows are grouped into upper half and lower half sections. The s...
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WO/2002/047296A1 |
An analog filter comprises first and second arithmetic operation sections (2¿-1?, 2¿-2?) connected in series and each composed of processing circuits connetected in series. Each processing circuit includes an S/H circuit of plural stag...
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WO/2002/043247A1 |
The invention relates to a method and system for implementing a digitally controlled sample and timing clock in a system performing analog and digital signal processing. According to the method, as the timing clock of the digital signal ...
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WO/2002/043249A1 |
A step size is generated for use in a continuous variable slope delta (CVSD) demodulator by determining a likelihood that a group of one or more coded bits includes an erroneous bit. The step size is then generated as a function of the l...
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WO/2002/037686A2 |
A control mechanism that can be used to control a $g(S)$g(D) to provide the required level of performance while reducing power consumption. The $g(S)$g(D) ADC is designe dwith multiple stage (i.e., loops or sections), and provides improv...
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WO2001010034A9 |
A modulator (10) having a continuous-time filter (12) receives an analog input signal (14) and a negative feedback signal (26) from a digital-to-analog converter (18). A desired portion of the input analog signal (14) has a bandwidth cen...
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WO/2002/029425A1 |
A RF power measurement circuit for measuring RF power of a pulsed RF input signal has a sigma-delta ADC circuit and an AND gate for controlling delivery of clock pules to a clock input of the ADC circuit. The clock pulses are delivered t...
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WO/2002/027919A2 |
Signal correction in a bipolar transistor circuit having a base-emitter voltage and a non-linear output signal corresponding to a detectable characteristic is improved by correcting non-linearity in the signal at third and/or higher-orde...
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WO/2002/027953A1 |
The invention relates to a multi-standard receiver adopted to a plurality of wireless communication standards and comprising: receiving means; TDD switch means and a plurality of bandpass filter; a plurality of LNA means; mixer means; ba...
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WO/2002/027944A2 |
A circuit topology and method for converting a digital input signal to an analog output signal employs a modified sigma-delta loop and a DAC, and operates with improved accuracy over a wide frequency range. A loop filter such as a digita...
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WO/2002/023732A2 |
Methods and systems for improved feedback processing in delta-sigma modulators, including single bit and multi-bit delta-sigma modulators, continuous-time and discrete-time delta-sigma modulators, and digital and/or analog feedback loops...
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WO/2002/023734A2 |
A bandpass $g(S)$g(D) ADC utilizing either a single-loop or a MASH architecure wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, a two-path interleaved reson...
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WO/2002/023731A2 |
Methods and systems for applying digital dither includes methods and systems for applying a digital dither in data converters, such as, for example, delta-sigma data converters. In an embodiment, an analog signal from a first path of a d...
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WO/2002/023730A1 |
A modulator circuit is disclosed having integrating stages (62). Each integrator stage (62) comprises a differentially structured operational amplifier (64) having a first restore switch (70) coupled across the input terminals, and a sec...
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WO/2002/023733A2 |
The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a multi-bit DAC. The digital sigma-delta modulator receives a digital input signal a...
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WO/2002/021526A1 |
Processing an audio signal is provided, which processing comprises conversion (5) of the audio signal into a digital signal by a noise-shaping modulation (7), compressive encoding (3) of the digital signal at a predetermined sampling rat...
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WO/2002/021698A1 |
A delta sigma modulator system includes a delta sigma modulator (9) including a summing circuit (3) having a first input connected to receive an input signal (2), loop filter circuitry (5) having an input coupled to an output of the summ...
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WO/2002/021525A1 |
Estimating a compression gain obtainable in compressing a given audio signal, comprising extracting a signal power in a selected frequency band of the given audio signal, and obtaining an estimation of the compression gain by correlation...
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WO/2002/019533A2 |
An apparatus and method of improving linearity of a multi bit delta sigma modulator in which the output of a multi-bit quantizer of a delta sigma modulator isconnected in a feedback loop to a converter where output is a higher frequencys...
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WO/2002/017495A2 |
Several delta-sigma modulator circuits and a single quantizer provide analog-to-digital conversionfor mulitple frequency bands. A wideband mode is provided by coupling an analog signal to bedigitized directly to quantizer. Narrowband mod...
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WO/2002/017050A2 |
A clock generator for automatic test equipment generates clock signals from a reference clock. To generate a desired clock signal, a clock generator produces a time-quantized signal having a period equal to an integer number of reference...
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WO/2002/015407A2 |
A method and arrangement for bit-synchronizing a $g(S)$g(D)-modulator with pre-filter to an incoming single bit bitstream. One or more of the integrator states of the $g(S)$g(D)-modulator are corrected by a signal which is calculated fro...
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WO/2002/013473A1 |
Apparatus for reducing DC offset in a signal path of a conversion system comprising a front end circuit for providing an input signal having an a DC offset; an amplifier system coupled to the front end circuit to receive and amplify the ...
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WO/2002/009292A2 |
An adaptive sigma-delta modulation and demodulation technique, wherein a quantizer step-size is adapted based on estimates of an input signal to the quantizer, rather than on estimates of an input signal to the modulator.
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WO/2002/007321A1 |
A digital signal encoding apparatus for encoding one-bit signals generated by delta-sigma modulation through n channels (n$m(G)) comprising a channel combiner (6) for combining the scramble outputs from a scrambler (L4) and a scrambler (...
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WO/2002/005432A2 |
In a sigma-delta modulator the feedback circuit (4, 5) has an adjustable feedback factor controlled by an adjusting member (6) for adjusting the feedback factor of the feedback circuit.
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WO/2002/003747A2 |
A combination of an electret microphone (1) and a sigma-delta A/D converter (9, 5, 7, 8). The sigma-delta A/D converter has a DC feedback loop (8) which provides the bias current (IDC) for the junction FET (2) of the electret microphone....
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WO/2002/001724A2 |
The invention relates to a digital-analog converter, especially for mobile radiotelephone base stations, comprising a D flip-flop and a modulator. Said D flip-flop is clocked with a clock signal. A digital input signal is delivered to th...
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WO/2001/097384A2 |
Distortion and noise in high power digital PWM amplifiers is reduced by measuring the difference between the desired output signal and the actual output signal on a pulse by pulse basis. This analog error is converted into a digital sign...
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WO/2001/093430A1 |
The present invention relates to a sigma-delta modulator, which is operative in different standard modes for processing communication signals of different communication standards. The modulator comprises a 1-bit quantizer and a multi-bit...
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