| Document |
Document Title |
|
WO/2003/100983A1 |
A feedback noise - shaper (500) of an order of at least three implements a first pole set defining a signal transfer function (502, 504) of a selected corner frequency and a second pole set having at least one pole at a frequency at leas...
|
|
WO/2003/098808A1 |
An arrangement (100) and method for sigma-delta analog-to-digital conversion by providing parallel translating sigma-delta analog-to-digital converters (21, 22) and summing their outputs to produce a digital output signal having a bandwi...
|
|
WO/2003/096541A1 |
An analog to digital converter (108) includes a cross switch array coupled between an input switch array and an integrator configured to alternately transfer charges from a first input capacitor and a second input capacitor to a first in...
|
|
WO/2003/096542A1 |
A digital-analog converter includes a counter (13) for performing counting operation according to clocks (CK1, CK2), a comparator (12) for comparing the count value to a digital input value and outputting the clocks (CK1, CK2) until the ...
|
|
WO/2003/094356A1 |
A sigma-delta analog-to-digital converter (10) having DEM (14) facilitated data weighted averaging to select specific unit elements of a negative feedback loop digital-to-analog converter (15), which DEM (14) is comprised substantially o...
|
|
WO/2003/091933A1 |
An integrator circuit comprises an operational amplifier which has a transistor stage (1) with an input terminal (4) and an output terminal (3), a feedback capacitor (2) connected between the input terminal (4) and the output terminal (3...
|
|
WO/2003/084074A1 |
A method and system for an adaptive sigma-delta ($g(S)-Δ) modulator with one bit quantization that improves the signal-to-noise (SNR) of a $g(S)-Δ modulator is presented. A difference signal is produced representing the difference betw...
|
|
WO/2003/084073A1 |
In a high order delta sigma modulator stage having integrators (1401, 1402) with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a ...
|
|
WO/2003/081774A1 |
An adaptive proportional integral control loop (209, 210) provides an accurate measurement of input ot output sampling rates for use in asynchronous sampling rate conversion. An input counter (200) counts inputs samples and its output is...
|
|
WO/2003/077529A2 |
An Nth-order shaping coder with multi-level quantization and dithered quantizer. The coder (500) is inherently stable and produces a purely white quantization error spectrum. In one exemplary embodiment, the coder is first order, and an ...
|
|
WO/2003/077424A1 |
A delta-sigma modulator (100) comprising a number of integration stages (110) and having a feed-forward path (114) from a signal input section (102) to the signal path prior to a final integration stage (118), so as to reduce processing ...
|
|
WO/2003/075603A2 |
A digital microphone has a transducer for generating an analog signal representing an acoustic signal, and a single bit sigma−delta modulator analog−to−digital converter of order greater than one for generating a digital output sig...
|
|
WO/2003/075466A1 |
The invention relates to a method for reducing a data set consisting of process data which is to be transmitted from a field device. The process data comprises information on the operating state of the field device and/or information on ...
|
|
WO/2003/065587A2 |
A first and second signal source are coupled to an analog output in a digital input signal dependent configuration. The signal sources so that a contribution of their source signals adds up in a first or a second direction when the digit...
|
|
WO/2003/065590A2 |
The A/D converter has a digital output for outputting a digital output signal selected from a set of three or more available values. A feedback loop generates the digital output signal so that a time averaged difference between an analog...
|
|
WO/2003/061136A1 |
A method and apparatus for a pulse width modulated (PWM) signal (30, 130) is provided. The input is a digital signal which is a modulated signal (24, 124). In the illustrated form, the modulated input signal is either a PDM signal or a P...
|
|
WO/2003/058820A2 |
The invention relates to a method for interpolating, for the purpose of hodometry and/or goniometry, at least two position-dependent, periodic analog signals that are dephased relative each other and that are generated by scanning a meas...
|
|
WO/2003/056701A1 |
The invention relates to a sigma−delta N−phase keying modulator having non−uniform polar quantisation. According to one embodiment of the invention, a quantiser produces a quantised output so that it represents a symbol, selected f...
|
|
WO/2003/052923A2 |
In a digital IF downconversion circuit, in-phase and quadrature signal components are processed in the form of a single serial digital bit stream through a set of simple logic in combination with a reconstruction filter. A source digital...
|
|
WO/2003/052941A2 |
The invention relates to a sigma-delta modulator for converting digital input signals x(k). Said modulator comprises a first feedback loop of a spectrally formed output signal y(k) of the sigma-delta modulator and a second feedback loop ...
|
|
WO/2003/052939A2 |
The invention relates to a Sigma Delta A/D converter (2) for generating an N-bit digital output signal (4) on the basis of an analog input signal (6), comprising a control loop which comprises an N-bit A/D converter (2) for generating th...
|
|
WO/2003/052938A2 |
The invention relates to a sigma-delta converter for converting a digital input signal x(k) into an analog output signal y(t) with noise suppression within a useful band. Said sigma-delta converter comprises a principal path containing a...
|
|
WO/2003/046888A1 |
The invention relates to a method of decoding a delta modulated signal which has been encoded using an adaptively varied encoding step size. The decoding method comprises receiving the delta modulated signal over an erroneous channel, de...
|
|
WO/2003/043198A2 |
A bandpass sigma-delta modulator using acoustic resonators or micro-mechanical resonators. In order to improve resolution at high frequencies, acoustic resonators. In order to improve resolution at high frequencies, acoustic resonators o...
|
|
WO/2003/043199A2 |
A delta-sigma modulator has a first node at which is produced a difference signal equal to the difference in magnitude between a continuous time analog signal and an analog feedback signal generated from a digital output signal; an integ...
|
|
WO/2003/043197A1 |
Sigma-delta modulation is provided, comprising feeding an input signal to a first SDM, subtracting the output of the first SDM from the input signal, filtering the output of the subtracting to obtain a filtered signal, delaying the input...
|
|
WO/2003/043200A2 |
A Delta-Sigma Analog-to-Digital Converter (ADC) that can have a very high sampling rate (over 100 GHz) and which is preferably optically sampled to help achieve its very high sampling rate. The sampling rate can be many times higher than...
|
|
WO/2003/039007A1 |
A D&sol A converter for removing satisfactorily distortion by PWM even when a sampling frequency is lower than a signal frequency. A D&sol A converter provided with a pulse width modulation signal output circuit for outputting a pulse mo...
|
|
WO/2003/039006A2 |
A method of, and a converter for, converting an analogue input signal (X) to a digital output signal (Y) by incremental-delta conversion in which, at clock intervals, a non-uniform quantizer (7) produces digital quantizer signals, a digi...
|
|
WO/2003/036787A1 |
The invention relates to a sensorless commutation of a direct-current motor. To allow an exact, easy to design, flexible, and highly integratable circuit arrangement for commuting motor devices, analogue phase detectors are replaced by d...
|
|
WO/2003/032496A1 |
Method and arrangement for converting the sample rate of a higher sample rate discrete time signal to a lower sample rate discrete time signal or vice versa. A recursive signal processing algorithm with low pass filtering function is use...
|
|
WO/2003/030369A2 |
A multimode communications device includes an RF section and an analog-to-digital converter (ADC) located in a receive path between the RF section and a baseband section. The ADC includes a programmable signal converter core operable to ...
|
|
WO/2003/030372A1 |
A Multi-Rate Analog-to-Digital Converter (19) is coupled to a single crystal oscillator (17) as a reference clock and has at least two separate channels arranged to sample and convert input data at two differing clock rates. Each channel...
|
|
WO/2003/030373A1 |
A signal amplification apparatus in which an input signal is subjected to delta−sigma modulation and the resultant signal S1 is pulse−width modulated to obtain a PWM signal S2, which is amplified to a signal S3 of a predetermined siz...
|
|
WO/2003/023970A2 |
A method of encoding a first stream of digital signal data words d(k) is provided. A most recent value of the first stream of digital signal data words is received and memorized. A previous value of the first stream of digital data words...
|
|
WO2002025817A9 |
A system and method for reducing distortion (52) in a pulse width modulated digital system by selectively implementing linearization (46). The linearization is implemented computationally efficient, using no division operations. A freque...
|
|
WO/2003/017496A2 |
A multiplexed signal processor is described as having an input circuit for receiving multiple input signals. A modulator processes a selected input signal to produce a representative digital output. The modulator includes an integrator t...
|
|
WO/2003/015268A2 |
Analog FIR-filter comprising an asynchronous $g(S)Δ modulator (AM) generating amplitude-discrete time-continuous pulses, a sequence of delay cells (C¿1? ... C¿n?) for delaying said amplitude-discrete time-continuous pulses and means (...
|
|
WO2002103609A9 |
A variable modulus interpolator (1) for interpolating a fractional part of a rational number by which a reference frequency is to be divided in a multi-divisor divider in a variable frequency synthesiser comprises a third order sigma-del...
|
|
WO/2003/005662A1 |
A digital IF to base band demodulator (120) includes delta sigma samplers (202, 204) for sampling two channels of an IF signal at a sampling rate that is substantially higher than the Nyquist rate for the IF signal. A first pair of decim...
|
|
WO/2003/005570A1 |
A digital &Dgr Σ modulated signal produced by a quantitizer (1c) in a &Dgr Σ modulation processing unit (1) is put into a feedback loop before inputted to a power switch (2) and converted into an analog signal by a D&sol A converter (1...
|
|
WO/2003/003789A2 |
A method and apparatus for minimizing latency in digital signal processing paths. One example is an active noise cancellation device. The system includes a digital closed feedback loop having a forward path and a feedback path. The forwa...
|
|
WO2001067591A9 |
An interface circuit for converting a digital signal to an analog signal. The interface circuit includes a time response adjustment circuit, a modulator, and a filter. The time response adjustment circuit receives the digital signal and ...
|
|
WO/2003/001675A2 |
An N-level quantizer circuit (14) has an analog input terminal and N-1 digital output terminals, and includes a sampling circuit (SW samp) coupled to the input terminal for providing a sampled input voltage signal; at least one preamplif...
|
|
WO/2003/001674A2 |
A multilevel quantizer (14) is provided in combination with dynamic element matching DEM (20) circuitry in a multibit sigma-delta modulator (10). The DEM circuitry is implemented in a divided manner as two major component parts: at least...
|
|
WO/2003/001669A1 |
A decimator is provided that selectively varies the output sampling rate of an integer decimating device, such that the average output sampling rate corresponds to a desired output sampling rate. The output sampling rate varies such that...
|
|
WO/2002/103916A2 |
According to the invention, oscillating signals are generated from analog signals by providing an analog signal having a variable slope or amplitude to a circuit with a variable operating point and having a transfer function characterize...
|
|
WO/2002/101932A1 |
The invention concerns a passband Sigma-Delta analog-to-digital converter comprising a first resonator (101) and a second order second resonator (102), preferably of second order, whereof the respective central frequencies are adjustable...
|
|
WO/2002/101931A2 |
A pipeline AD converter comprising a cascade of AD-converter stages, whereby the sampling noise generated by a former stage of the cascade is AD-converted by the next stage in the cascade and the digital signals of the stages are combine...
|
|
WO/2002/095936A1 |
An intermediate voltage of a power supply voltage used for amplification of an audio signal of a first signal line OUTL and OUTR is generated and this intermediate voltage is applied as a reference signal voltage to a second signal line ...
|
