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WO/2000/052867A1 |
A system for reducing sensitivity of an integrated circuit chopper-stabilized amplifier to intermodulation applies a pseudo-random sequence signal (11A) to an LSB of a first input of a first adder. An error feedback (18) is applied to a ...
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WO/2000/046610A1 |
Pin slice circuitry used in automatic test equipment is disclosed. The pin slice circuitry includes a portion implemented using CMOS technology and a portion implemented using bipolar technology. The CMOS portion includes a plurality of ...
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WO/2000/044098A1 |
An analog-to-digital converter system [50D] processing an input signal $i(g), which can be either a discrete-time or a continuous-time signal. A first quantizer [154] generates a first digital signal $i(d)¿0?$i((k)), representing the su...
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WO/2000/041322A1 |
The invention relates to a circuit for a multi-standard communications terminal. For receiving radio signals (FS1, FS2), said circuit has a high frequency part (1) with a receiving mixer stage (2) and a signal processing circuit (3; 3') ...
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WO/2000/041311A1 |
Digital-to-analog conversion circuitry (100) is shown including a path for processing data in a 1-bit format. First portion of an analog finite impulse response filter (300) includes pre-selected number of delay elements (301) for receiv...
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WO/2000/039538A1 |
The invention concerns a device for ultrasonic measurement of a fluid flow rate comprising a first and a second transducer (1, 2) placed in the fluid whereof the flow is to be determined. Said device comprises means for processing (21) a...
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WO/2000/038327A1 |
A delta sigma (also called sigma delta) analog-to-digital converter circuit (30) has an integrator input (36) couplable to an analog signal V¿dc? and has a clocked controller (32) generating a converted digital output (38) representing ...
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WO/2000/038334A1 |
The present invention relates to a transmission circuit of a radio frequency signal, intended to receive an input signal (IN), comprising: a first frequency converter (FC1), having reference inputs intended to receive at least one differ...
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WO/2000/036750A1 |
An inventive high-resolution Delta-Sigma analog-to-digital converter (15) using a Continuous-Time implementation having suppressed sensitivity to clock jitter. The inventive method and apparatus suppresses the sensitivity to jitter by th...
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WO/2000/035096A2 |
The invention relates to an analog-digital converter which comprises a multitude of integrating circuits, a 1 bit analog-digital converter and a 1 bit digital-analog converter. The multitude of analog integrating circuits are connected i...
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WO/2000/035097A1 |
The present invention correlates (204, 710) noise from a delta sigma modulator (104, 702) with noise from the same modulator passed through a nonlinear block (202, 706) whose purpose is to isolate the imperfection being measured. Once th...
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WO/2000/031877A2 |
The invention relates to a sigma delta D/A-converter (300) with N steps, the nth step, with n = 1, 2, 3... N, comprising the following; a first adder (10), which adds a useful signal x(k) (12) and an error signal err¿n?(k-1) to give an ...
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WO/2000/031879A1 |
The invention relates to a circuit configuration for quantisation of digital signals and for filtering quantisation noise. Said circuit configuration comprises a multitude of digital control loops connected in series and having quantiser...
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WO/2000/025428A1 |
The invention concerns the field of sigma-delta modulators. More particularly it concerns a sigma-delta modulator presenting a propagation delay $g(D)t between an analog-to-digital converter (40) input and a digital-to-analog (60) output...
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WO/2000/022735A1 |
A radio receiver comprises an input (10) coupled to first and second quadrature related low-IF frequency translation stages (20, 21) generating IF signals at substantially half the channel bandwidth or channel spacing. The IF signals whi...
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WO/2000/021337A2 |
An integrated, multi-input audio mixer (80) receiving a plurality of analog input signals (Ain-1AinN), internally digitizing the analog input signals, digitally processing and mixing the digitized input signals and producing both digital...
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WO/2000/019615A2 |
A delta sigma modulator (340) of at least second order includes correction means (342, 344) applied to each feedback loop (54) in the modulator, to account for systemic nonlinear output distortions. Since the output distortion is nonline...
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WO/2000/016181A1 |
The invention concerns a method and a device for generating a random signal. It also concerns a digital-to-analog converting system using such a signal. The invention also concerns a digital-to-analog converting system using such a rando...
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WO/2000/008765A2 |
A delta-sigma modulator (196) comprising a first quantizer (202) providing a first digital signal d¿0?(k) representing the input signal g(t); a loop filter (198) with input signal paths (200); a loop quantizer (160) providing a correcti...
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WO/2000/008764A1 |
A radio frequency signal is received by using a sigma-delta analog-to-digital converter to sample the radio frequency signal at a sampling rate and to generate therefrom 1-bit digital samples representing a digital intermediate frequency...
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WO/2000/007301A2 |
A hardware-efficient transceiver. The transceiver (80) includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital ...
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WO/2000/002318A2 |
A multi-bit digital/analog converter with M delta-sigma modulators and a sort logic that selects a number of DA elements according to the input signal of the converter so that the DA elements selected are associated with the quantifiers ...
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WO/2000/001074A2 |
A receiver with an integrated mixer/Sigma-Delta Modulator configuration for digitizing a relatively low-bandwidth signal modulated on a high-frequency carrier, for example in a radio receiver. The Sigma-Delta Modulator has a continuous-t...
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WO/2000/001072A1 |
In the illustrative embodiment, the inventive system includes a low-bit digital-to-analog converter (68) for converting a first signal at a reference frequency to a digital signal. A delta-sigma converter is included for suppressing nois...
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WO/1999/065147A1 |
Hardware for an over-sampling A/D, D/A converter capable of operating under either software handling a first method having a fixed over-sampling ratio or software handling a second method having a variable over-sampling ratio, wherein a ...
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WO/1999/063660A1 |
In order to increase the resolution of signals input to a power amplifier, this system includes a power control circuit which utilizes sigma delta modulated values which are stored in a memory device. These values, after retrieval from a...
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WO/1999/060705A1 |
A flash converter (104) is preceded by an accurate continuous-time error amplifier (102) operating on the difference between the input signal and a feedback DAC (114). The DAC output is operatively coupled to the amplifier virtual ground...
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WO/1999/057671A1 |
A lossy integrator using an amplifier (3) and having a capacitor (37) voltage coefficient errors reduced by providing oppositedly oriented first and second feedback capacitors (33 and 43) in a switched capacitor feedback circuit (11A).
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WO/1999/056446A2 |
A D/A converter (DAC) is described having interpolation means (1) and filter means. Further the D/A converter comprises a noise shaper (3) implemented as a reduced sample rate (RSR) sigma-delta modulator, and controlled by clock means. T...
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WO/1999/049578A1 |
Oversampling DACs suffer tend from idle channel tones when converting low level input signals (192) in spite of the noise-shaping features of the Delta-Sigma modulator (150). In the proposed DAC system a dither signal, which is preferabl...
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WO/1999/048202A2 |
An analog-to-digital converter (10) comprises a modulator (12) connected to an analog input signal, a decimator (14) connected to the output of the modulator, a normalizer (16) connected to the ouput of the modulator and forming a digita...
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WO/1999/046860A1 |
An asynchronous mode sigma-delta modulator circuit is usable, for example, at each pixel of a CMOS image sensor. The asynchronous sigma-delta modulator includes a comparator circuit (MND0, MND1, MND2, MPD1, MPD2) whose output switches to...
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WO/1999/044289A1 |
A digital to analogue converter (DAC) system (30) is described which has a plurality of weighting elements (40) where some of the weighting elements have a different nominal weight from other elements. In a preferred arrangement pairs of...
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WO/1999/039440A2 |
The device for processing a digital signal comprises an input (10) for receiving the digital signal and an output (18) for supplying an output signal. The device further comprises filter means (14) coupled to the output (18) for deriving...
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WO/1999/035746A1 |
A noise cancellation circuit and quadrature downconverter for use in conjunction with a bandpass receiver. The noise cancellation comprises at least one bandpass decimator and a summer. The output from each loop of a sigma-delta analog-t...
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WO/1999/033266A2 |
Method and arrangement for watermarking an audio or video signal. The signal is encoded by an encoder (6) which includes a feedback loop (64) to control the encoding process, such as a DPCM encoder or a (sigma-)delta modulator. The water...
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WO/1999/030428A1 |
A receiver comprising a sigma-delta analog-to-digital converter ($g(S)$g(D) ADC) can be utilized in one of four configurations, as a subsampling bandpass receiver, a subsampling baseband receiver, a Nyquist sampling bandpass receiver, or...
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WO/1999/030427A1 |
A programmable dynamic range receiver which provides the requisite level of performance at reduced power consumption. The $g(S)$g(D) ADC within the receiver is designed with one or more loops. Each loop provides a predetermined dynamic r...
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WO/1999/026077A1 |
An improved digital fluxgate magnetometer (20) that uses digital logic and a high resolution digital to analog converter (40) to digitize a magnetic signal for use by signal processing algorithms. The magnetometer includes an oscillator ...
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WO/1999/020004A1 |
The invention relates to digital signal processing and specificly to level control of a pulse density modulated (PDM) signal generated by a sigma-delta modulator. A single-bit pulse density modulated PDM signal is generated by a first si...
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WO/1999/018691A1 |
The present invention provides a simple all digital method and apparatus (fig. 4) for determining the phase of a first clock signal (Fs) relative to a second clock signal (Fs). The first clock signal (Fs) may be a digital approximation o...
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WO/1999/018671A1 |
A method, and apparatus are provided for reducing distortion in a dynamically delayed digital sample stream (34, 40) of an imaging system (10). The method includes the steps of delta sigma modulating an input analog signal of the imaging...
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WO/1999/014860A1 |
A bandpass $g(S)$g(D) ADC utilises either a single-loop (10) or a MASH architecture (12, 100, 121). Resonators are implemented as either a delay cell resonator (131), a lossless discrete integrator resonator (132), a Forward-Euler resona...
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WO/1999/014859A1 |
A frequency synthesizer has a phase locked loop, a $g(D)$g(S) modulator, and a filter. The phase locked loop includes a frequency divider that controls the frequency of the phase locked loop output signal. The output of the $g(D)$g(S) mo...
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WO/1999/012264A2 |
Sigma-delta modulator in which the gain stage (20) of the input network and the gain stage (22) of the feedback network are regularly interchanged ('chopped'). This averages out the difference between the two gain stages, thus defining t...
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WO/1999/009491A1 |
A delta-sigma analog/digital converter is provided for operating in the analog domain to generate a digital value that is to be processed by a digital signal processor (DSP) (26) to provide on the output a digital output. Each data node ...
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WO/1999/008388A2 |
A method and arrangement for converting an analog input signal into a digital output signal. The analog input signal is converted into a duty cycle modulated square wave. For recucing the communication rate of the digital output signal a...
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WO/1999/008389A2 |
Known is a digital communication device having a dual conversion architecture. A first RF-mixing stage is provided followed by a second, quadrature, mixing stage of which output signals are sampled by means of an analog-to-digital conver...
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WO/1999/008378A2 |
The device for amplifying digital signals comprises an input electrode (10) for receiving a digital signal. The device further includes a subtraction unit (12) for subtracting at least two signals from each other, and the input electrode...
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WO/1999/005806A1 |
An oversampled, noise shaping signal processor (300) is described having at least one integrator stage (306) in the loop. A sampling stage (310) is connected coupled to the at least one integrator stage. The sampling stage samples an ana...
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