To provide a semiconductor storage device which provides the timing of a signal for controlling a read register and a write register with flexibility and has a function for changing data sequences.
The device is equipped with a memory core part 2, an I/O circuit 4 for inputting and outputting serial data, shift register parts 3 having the read register for receiving serial data of a plurality of bits from the I/O circuit 4 and converting the serial data into parallel data, and the write register for receiving parallel data of a plurality of bits from the memory core part 2 and converting the parallel data into serial data, and a signal generation circuit 6A for generating a plurality of first control signals that give conversion timing for each bit at the time of serial/parallel conversion and generating a plurality of second control signals that give conversion timing for each bit at the time of parallel/serial conversion. The signal generation circuit 6A controls rise or fall timing of the plurality of first and second control signals.
| JPH0877796 | SEMICONDUCTOR MEMORY |
| JPS5199418 | TEIDENJINO IC MEMORIIHOJIKAIRO |
| JP2006236579 | SEMICONDUCTOR MEMORY DEVICE |
YONETANI KAZUHIDE
HISADA TOSHIKI
KOYANAGI MASARU
Sadao Muramatsu
Atsushi Tsuboi
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai