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WO/2010/084124A1 |
A method of detecting a phase difference between a circuit output signal and a reference signal is useful in all digital phase locked loops. A plurality of feedback signals are generated from the circuit output signal by means of a proce...
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WO/2010/083920A1 |
A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to com...
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WO/2010/085008A1 |
The present invention relates to a clock data recovery apparatus having all circuits thereof digital-circuitized through a digital filter and a digitally controlled oscillator (DCO). A DCO according to the present invention has a chain o...
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WO/2010/083744A1 |
A low power consumption control circuit comprises a receiving circuit (101), a control chip (102), and a clock generation control circuit (104). The receiving circuit (101) is connected with the control chip (102) which is connected with...
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WO/2010/081188A1 |
A method for extending the range for tracking phase errors in a phase lock loop, the method including the steps of: measuring a raw phase error; comparing said raw phase error with a previous phase error to compute a phase difference; ca...
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WO/2010/080176A1 |
In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by sourc...
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WO/2010/077981A1 |
A power generator system and apparatus that uses a frequency synthesizer in conjunction with an oscillator to lock both frequency of a drive signal with a reference signal. The oscillator center frequency is different from the nominal ge...
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WO/2010/068604A2 |
An integrated circuit includes a linearizer circuit in which excessive delay is compensated. The linearizer circuit includes a power amplifier, forward and feedback paths, and a microprocessor. A signal from the power amplifier is routed...
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WO/2010/068679A2 |
A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described. The DPLL includes highpass and lowpass modulation paths that support wideband and narrowband modulation, respectively, of the f...
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WO/2010/068503A1 |
A local oscillator (LO) module comprises a local oscillator and a feedback circuit. The local oscillator, biased at a supply voltage, generates a local oscillator signal having a duty cycle. The feedback circuit makes an absolute adjustm...
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WO/2010/067495A1 |
A mode determining circuit determines existence/absence of an electric system state change which causes a frequency change of a system control clock, and a clock switching circuit switches the system control clock from a system clock to ...
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WO/2010/060859A1 |
The invention relates to an optoelectronic device for frequency discrimination, characterised in that it comprises: an input for an optical wave pair comprising a first wave at a first frequency (F1) and a second wave at a second frequen...
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WO/2010/059331A1 |
A jitter correction operation, wherein a first timing signal is generated in a locked-loop circuit to time a transmission of a data signal within a corresponding transmit circuit. A second timing signal is generated within another locked...
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WO/2010/057520A1 |
In a self injection locked voltage controlled oscillator arrangement (1), a pair of coupled first and second voltage controlled oscillator devices (21,22) are arranged on a chip (2), an amplifier device (23) is arranged on the same of th...
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WO/2010/059032A2 |
The present invention relates to a phase frequency detector (PFD) (100) for use as one of the blocks in a phase-locked loop. The PFD of the present invention has zero dead zone, has a simpler structure with a minimum number of transistor...
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WO/2010/056912A1 |
Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump leakage current in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage...
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WO/2010/056813A1 |
A PLL-based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The system may include two primary functional blocks -- an input PLL with its reference path containing an integer divi...
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WO/2010/056814A1 |
A multi-branch frequency translation system converts a plurality of independent input clocks to a common frequency. One of the converted clock signals is selected as a dominant clock. The remaining converted clock signals are edge-synchr...
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WO/2010/055619A1 |
Provided is a frequency synthesizer which can suppress degradation of the transmission performance when applied to a radio communication device which can switch the transmission power from one to another and execute transmission with an ...
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WO/2010/056913A1 |
Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump output noise in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage co...
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WO/2010/056840A1 |
A phase locked loop (PLL) based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The PLL is configured as an all digital PLL and includes a bang-bang phase frequency detector, digi...
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WO/2010/052595A1 |
Described is an apparatus that includes a frequency source and a plurality of time domain direct digital synthesizers each having an input connected to an output of the frequency source and an output providing an output frequency signal....
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WO/2010/052216A1 |
The present invention relates to the domain of video equipment. Specifically it relates to a transmission device able to transmit packets in a packet communication network, said device comprising the means (EXS) to extract clock signals ...
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WO/2010/051417A1 |
A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outpu...
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WO/2010/047005A1 |
A digital PLL circuit for providing as an output a clock signal having a frequency obtained by multiplying the frequency of a reference signal by a frequency control word (frequency ratio). In the digital PLL circuit, an RPA circuit (101...
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WO/2010/043614A1 |
The invention relates according to a first aspect to a device (1) for reconstructing a clock signal from a baseband serial signal (NRZ-D), comprising: - a pulse generating circuit (2) adapted for generating pulses at each transition, ris...
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WO/2010/045348A1 |
Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a n...
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WO/2010/041163A2 |
A circuit arrangement is described comprising a first receiver configured to receive a first input signal, a second receiver configured to receive a second input signal, a first signal generator configured to generate a first pulse signa...
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WO/2010/041780A1 |
There is provided a bit-transition point extraction circuit device that includes: a predetermined current source transistor; a pair of transistors connected with a source which is biased to the current source transistor and is applied wi...
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WO/2010/041864A2 |
An apparatus and a method for calibrating a Voltage Controlled Oscillator (VCO) using a fast frequency comparison based on phase manipulation are provided. The calibrating apparatus includes a phase shifter for comparing an input referen...
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WO/2010/041159A1 |
The present application relates to a digitally controlled oscillator comprising an inductive element. The digitally controlled oscillator comprises a first capacitor array comprising first unit capacitors. The digitally controlled oscill...
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WO/2010/042763A1 |
A clock clean-up phase-locked loop (PLL) that may reduce spurs and improve performance of a receiver is described. In one exemplary design, an integrated circuit includes a PLL and an analog-to-digital converter (ADC). The PLL receives a...
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WO/2010/039638A2 |
Techniques involving the generation of signals at particular frequencies are disclosed. For instance, an apparatus may include an oscillator module, a synthesizer module, and a control module. The oscillator module produces an oscillator...
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WO/2010/038456A1 |
Provided is a technique capable of instantaneously or previously determining a state in which PLL control does not normally operate in a frequency synthesizer which subjects the frequency signals from a voltage control oscillation sectio...
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WO/2010/039365A1 |
In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed reference clock signal may be maintained by d...
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WO/2010/035876A1 |
Provided is an oscillation circuit. The oscillation circuit supplies predetermined oscillation signals to a generating circuit having a divider, a phase comparator and a generator. A clock signal generating section generates clock sign...
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WO/2010/032380A1 |
The oscillating circuit (100) includes a variable frequency oscillating circuit (10) for generating a clock signal (CK) whose frequency increases in response to an up-signal (UP) and decreases in response to a down-signal (DOWN), the fre...
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WO/2010/032699A1 |
An input signal having a binary waveform is reproduced at high speed and low power consumption. A clock reproduction circuit is provided with an equalizing circuit for equalizing the input signal having the binary waveform to a duo-binar...
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WO/2010/031840A1 |
The present invention relates, according to a first aspect, a method for reduction of the difference in phase between a first signal and a second signal, a phase locked loop PLL1 receiving the samples PCRr from the first signal and produ...
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WO/2010/033308A2 |
The present invention relates to a mixed mode electronic circuit that implements a PLL cell that employs an auto-range algorithm to lock to a wide range of input reference signals.
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WO/2010/032830A1 |
A digital phase comparator of high resolution is provided without increasing the circuit area and the power consumption. A delay circuit array (21_1 to 21_n–1) generates delayed signals (CKC(1) to CKC(n–1)) obtained by delaying an i...
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WO/2010/032328A1 |
A PLL circuit comprising a phase comparator (4) for detecting a phase difference between a first signal and a second signal, a first oscillation circuit (1) for providing a standard signal to the phase comparator as the first signal, and...
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WO/2010/031279A1 |
A digital phase locked loop and a method for eliminating glitch are provided, which belong to the electrical technical field. The digital phase locked loop includes a trigger and a delay line. The method includes: the trigger receiving a...
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WO/2010/033853A1 |
Techniques for adaptively calibrating a TDC output signal in a digital phase-locked loop (DPLL). In an exemplary embodiment, a calibration factor multiplied to the TDC output signal is adaptively adjusted to minimize a magnitude function...
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WO/2010/033436A2 |
A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a c...
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WO/2010/029114A1 |
A PLL circuit (1a, 1b) for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and...
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WO/2010/030688A2 |
In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden usi...
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WO/2010/029389A1 |
A semiconductor device (400) comprising clock gating logic (405). The clock gating logic (405) comprises clock freezing logic (410) arranged to receive a selected clock signal (415) and an enable signal (460). The clock freezing logic (4...
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WO/2010/025564A1 |
A method and system for fractionally converting sample rates. Fractional rate conversion for a transmit path of a transceiver is achieved by upsampling an input signal having a first sample rate by a first integer factor, removing aliasi...
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WO/2010/025563A1 |
A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final...
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