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WO/2010/144995A1 |
A device is provided having a local oscillator (LO) configured to generate a first signal comprising at least one of: timing information; frequency information; phase information; and combinations thereof. The device also has a LO error ...
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WO/2010/144996A1 |
A device is provided having a local oscillator (LO) configured to generate a first signal having timing information, frequency information, phase information or combinations thereof. The device also includes a prioritizer comprising at l...
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WO/2010/144912A1 |
Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derive...
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WO/2010/143363A1 |
Disclosed are a resonator and an oscillator using the same, capable of broadly and finely correcting the resonant frequency of the vibrating element. The resonator comprises a vibrating element (101), electrodes (4, 5) arranged with a cl...
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WO/2010/143241A1 |
A phase comparison circuit (111) counts the number of transitions of a reference clock (CKR1) and an oscillator clock (CKV1); sets , as the phase comparison period, the period until the number of transitions of the reference clock reache...
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WO/2010/141909A1 |
A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a DCO output signal and a reference clock and outputs a first stream of digital values. Quantization noise is reduced by clocking the TDC at a hi...
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WO/2010/139769A1 |
The invention relates to a radio-frequency circuit comprising: - a control unit; and - a phase-locked loop; wherein the control unit is arranged to determine an offset between an actual value of a reference frequency at the input to the ...
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WO/2010/138291A1 |
A phase lock loop utilizes a multiphase oscillator having a plurality of digital inputs. A plurality of DQ flip-flops, offset in time from each other generate a plurality of control signals to remove control phase information from the os...
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WO/2010/137419A1 |
A reference frequency generator device (11) is provided with a GPS receiver (21), a PLL circuit (31), a detector (28), a storage unit (29), and a control unit (22). The PLL circuit (31) controls the digital control oscillator (26) based ...
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WO/2010/135607A1 |
Methods and apparatus for self testing a multiband voltage controlled oscillator (VCO) are disclosed. A tuning voltage of the VCO is adjusted where the output of the VCO does not affect the input to the VCO. Frequency bands in the VCO ar...
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WO/2010/133752A1 |
An apparatus, a method and computer program, the apparatus comprising: a modulator (9) comprising a first input for receiving a data signal (27) and a second input for receiving an output signal (23) from a phase locked loop (5) wherein ...
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WO/2010/135397A1 |
In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is cou...
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WO/2010/134287A1 |
Disclosed is a PLL frequency synthesizer the phase noise characteristics of which are improved. To achieve this, in an ADPLL frequency synthesizer (100), a frequency characteristic adjusting unit (180) compares a predetermined threshold ...
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WO/2010/130596A1 |
This invention relates to a phase detection method. An input signal (51, 91, 111) is sampled (13, 14, 15, 16) for obtaining several samples (1, 2, 3) at different points in time which are defined by a clock (C). A phase control signal (4...
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WO/2010/131104A2 |
The present invention relates to a method for controlling the activation of a circuit (PRCU) clocked by a clock signal (CLK), the method comprising a phase of activating the circuit comprising simultaneous steps of increasing a supply vo...
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WO/2010/131528A1 |
Disclosed is a receiving device with which increases in circuit areas and cost, which are required for appropriate sampling, can be prevented. An A/D converter (2) converts a coherent signal serving as an analog signal into a digital sig...
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WO/2010/126567A1 |
A voltage controlled oscillator (VCO) includes a cross-coupled pair of n-type transistors and a cross-coupled pair of p-type transistors, wherein the ground-facing side of the n-type transistors are connected to the power-facing side of ...
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WO/2010/126845A1 |
A supply-regulated Phase-locked loop (PLL) is provided. The PLL comprises a supply-regulating loop, a voltage-controlled oscillator (VCO), and a programmable decoupling capacitor array for the VCO. The capacitance of the VCO decoupling c...
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WO/2010/126844A1 |
A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer ...
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WO/2010/126706A1 |
In a data transmission network, such as a passive optical network, the consecutive identical digit (CID) handling requirements may be reduced by providing a CID monitoring module at the transmitter end that monitors the number of CIDs in...
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WO/2010/118980A1 |
A phase-locked loop circuit comprising: an oscillator (20) configured to generate an output signal; an input (25) for receiving a reference clock signal; a delay cell (26) configured to delay the reference clock signal to generate a dela...
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WO/2010/113108A1 |
A low power frequency synthesiser circuit (30) for a radio transceiver, the synthesiser circuit comprising: a digital controlled oscillator (33) configured to generate an output signal (F0) having a frequency controlled by an input digit...
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WO/2010/115215A1 |
A system and method is disclosed that provides a technique for generating an accurate time base for MEMS sensors and actuators which has a vibrating MEMS structure. The accurate clock is generated from the MEMS oscillations and converted...
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WO/2010/115152A1 |
Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock ...
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WO/2010/113377A1 |
A digital FLL/PLL able to converge an oscillation frequency from a VCO to a desired frequency at a high speed even without setting a damping factor for each VCO gain. The digital FLL/PLL is provided with: a comparator for comparing a cha...
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WO/2010/108658A1 |
The invention relates to a method for generating two light waves (3, 11) which have stable frequencies relative to one another, in which method an accumulation of particles of a lambda system is illuminated by a control light beam (3) an...
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WO2010110184A1 |
A circuit able to achieve high frequency tracking performance while satisfying jitter/wander suppression performance. The circuit controls the loop gain of a PLL means (100) according to the results of processing a jitter/wander componen...
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WO/2010/108943A1 |
The present invention relates to a frequency synthesizer including: a first oscillator (1) controlled by a first control device, the first oscillator having a high quality factor that is greater than 300 and produces a first clock signal...
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WO/2010/108034A1 |
Techniques for providing transformer-based CMOS oscillators capable of operation with low voltage power supplies. In an exemplary embodiment, an LC tank is provided at the drains of a transistor pair, and the inductance of the LC tank is...
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WO/2010/108036A1 |
A wireless communication device incorporating a set of comparators and logic interrupt into the local oscillator generation circuit block is described. In one design, the local oscillator circuit block includes a RF VCO with coarse and f...
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WO/2010/107943A1 |
A method for self testing a multiband voltage controlled oscillator (VCO) is described. A first frequency band in a VCO is selected. An N value is selected for a frequency divider that produces a tuning voltage for the VCO that is betwee...
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WO/2010/104891A1 |
Techniques for setting a fine tuning input signal Vtune for a voltage-controlled oscillator (VCO) in a coarse tuning mode of the VCO. In an exemplary embodiment, the fine tuning input signal during coarse tuning mode is made temperature-...
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WO/2010/104980A1 |
A wireless communications method is provided. The method includes analyzing one or more channel conditions from a wireless communication and automatically adjusting a frequency tracking loop gain or a time tracking loop gain in view of t...
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WO/2010/103626A1 |
Provided is a clock generation circuit which performs a phase control in a wide range with a low power consumption. Provided also is a signal reproduction circuit using the clock generation circuit. A counter circuit (a divider circuit) ...
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WO/2010/104164A1 |
A first equidistant-clock signal group is used to sample a second clock signal, thereby generating a first phase difference signal. The second clock signal is delayed by equal intervals, thereby generating a second clock signal group, wh...
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WO/2010/101779A1 |
A crystal oscillator-based module, which includes a crystal resonator receiving a conditioned signal from a first bus and passing a resonator signal to a sustaining stage amplifier. A synchronization range expansion circuit is connected ...
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WO/2010/099855A1 |
The invention relates to a measuring apparatus having a synthesizer device (49c), at least two control devices (86c, 86d), and at least two controlled oscillators (64c, 64d). The synthesizer device (49c) comprises at lest one direct digi...
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WO/2010/097846A1 |
A phase adjustment circuit which obtains a clock of 50% Duty by applying two frequency division to a double-frequency clock, wherein a two-frequency-dividing circuit (40) having a first phase inversion function generates an intermediate ...
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WO/2010/097273A1 |
It is described an electronic device for generating a fractional synthesized frequency. The device comprises a multi-phase controlled oscillator adapted to generate, from a control signal, a plurality of signals phase-shifted each other ...
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WO/2010/092491A2 |
An integrated circuit (805) comprises frequency generation circuitry (800) for controlling a frequency source (810) for use in an automotive radar system. The frequency generation circuitry (800) comprises low-path modulation circuitry a...
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WO/2010/093961A1 |
A frequency synthesizer with multiple tuning loops, e.g., a fine tuning loop and a coarse tuning loop, is described. The fine tuning loop may operate over a limited tuning range and may have fine frequency resolution. The coarse tuning l...
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WO/2010/092438A1 |
An integrated circuit (105) comprises frequency generation circuitry (100) for controlling a frequency source (110) for an automotive radar system. The frequency generation circuitry (100) comprises a Phase Locked Loop (PLL) (115) arrang...
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WO/2010/093471A1 |
An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency, calibration circuitry configured to periodically cali...
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WO/2010/093158A2 |
The present invention relates to a receiving apparatus for a display-driving system, and more particularly, to a receiving apparatus having a delay locked loop-based clock recovery unit, in which a receiving unit is not provided with a p...
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WO/2010/089207A1 |
A method is provided for selecting an operating band of a voltage-controlled oscillator ("VCO") of a phase locked loop ("PLL") for which the lock frequency is closest to a center of the frequency range of the operating band. In such meth...
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WO/2010/091063A1 |
A device including a voltage regulator with an adaptive switching frequency circuit for noise-sensitive analog circuits, such as oscillatory systems with phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs) is described. In ...
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WO/2010/089208A1 |
A phase locked loop ("PLL") includes a voltage controlled oscillator ("VCO") operable to acquire and maintain lock at a selected output frequency of the VCO and control logic operable to perform steps in a method of selecting a frequency...
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WO/2010/089168A1 |
A phase-locked loop comprising; an oscillator configured to output an oscillating signal in dependence on the control signal at an input of the oscillator; a phase detector and loop filter configured to output a low frequency compensatio...
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WO/2010/086077A1 |
The present invention relates to, a method for assigning a target (CSG) to a configurable oscillator (VCO) of a phase-locked loop (PLL), the phase-locked loop (PLL) receiving samples (PCRr, PCR1r, PCR2r) of a first signal realised accord...
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WO/2010/087880A1 |
Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and m...
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