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WO/2011/077481A1 |
A radio apparatus comprises: a first receiver (12) that is a processing unit for amplifying and frequency converting a radio signal received via an antenna, thereby outputting an IF signal; a detector unit (15) for detecting a preamble s...
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WO/2011/075540A2 |
A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic sign...
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WO/2011/075051A1 |
A method of, and a system for determining a filling level of a product contained in a tank using a radar level gauge system, the method comprising the steps of: generating a transmission signal using first pulse generating circuitry outp...
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WO/2011/071953A1 |
A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to a...
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WO/2011/071954A1 |
A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO)...
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WO/2011/064122A1 |
A phase locked loop frequency synthesizer comprises a voltage controlled oscillator; a loop filter for supplying a control voltage to the oscillator; a phase frequency detector arranged to detect a phase difference between a reference si...
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WO/2011/064583A1 |
A battery powered device is able to maintain a clock value when the battery is removed for a short period. During a first time period, while the battery is in the device, clock pulses derived from a first oscillator are counted at a firs...
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WO/2011/061520A1 |
A phase locked loop (10) comprising: a tuneable oscillator (12); a mixer-based phase sensitive detector (18) to receive input signals from the tuneable oscillator (12) and a reference signal (20); a cycle slip detector (26) to receive in...
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WO/2011/062114A1 |
A frequency converter (192) is provided with a first direct digital synthesizer (1920) that receives a signal (REF1) of a predetermined frequency (f_master) as a clock signal, additionally receives an internal frequency setting signal (S...
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WO/2011/061293A1 |
A method of generating a first oscillator signal having a desired frequency in a first frequency range comprises generating in a voltage controlled oscillator unit (72) a second oscillator signal having a frequency in a second frequency ...
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WO/2011/056526A2 |
An ultra wide band (UWB) millimeter (mm) wave radar system (100) includes a signal source (105) having a control input (106), a GHz signal output and a frequency controlled output. (108) A control loop (146) is coupled between the GHz si...
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WO/2011/054242A1 |
A phase discriminator and a phase-locked loop circuit are disclosed. The discriminator comprises a first clock input circuit used for receiving a first clock signal and generating a first comparison signal to be output according to the f...
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WO/2011/051407A1 |
The invention relates to a device for generating clock signals, comprising a phase locked loop (100) including: - a controlled oscillator (101) capable of outputting a clock signal, - a plurality of phase comparators (102.1-102.4) capabl...
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WO/2011/053111A2 |
A read-out interface circuitry (ROIC) (10) connectable to a sensor (29) is provided, the ROIC (10) includes at least one phase detector circuit (20) to compare phase difference between an input reference signal and an output signal from ...
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WO/2011/050693A1 |
A locking method and system thereof are provided by the present invention, wherein the method includes the following steps: first, the locking system performs phase discrimination and conversion processing for a frequency-divided externa...
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WO/2011/045300A2 |
The invention relates to the field of radio communication devices and, more specifically, gateways connected to (i) a cellular radio communication network via a packet data communication network, such as an IP network, and (ii) cellular ...
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WO/2011/045280A1 |
The invention relates to an oscillator, and to a method for generating electric oscillations depending on a frequency control signal having a transfer oscillator circuit for generating the electric oscillations and a control loop for reg...
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WO/2011/041297A1 |
A continuous-rate clock and data recovery circuit includes a delay locked loop with a first integrator and a phase locked loop with a separate integrator. The delay locked loop and the phase locked loop are in a dual loop architecture. T...
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WO/2011/039835A1 |
Disclosed are a clock generation circuit and a signal reproducing circuit including the same, more specifically, a data determination/phase comparison circuit capable of performing data determination and phase comparison using a single-p...
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WO/2011/039656A1 |
A method includes generating a plurality of reference phases of a reference signal and selecting a sub-phase from each of the plurality of reference phases to form a set of selected sub-phases. In the method selecting operates in respons...
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WO/2011/035118A1 |
A method of calibrating oscillators is disclosed that includes searching, in an array storing an operational characteristic of the oscillator, for an index value that is associated with an output of the oscillator; determining that the o...
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WO/2011/032287A1 |
Described herein are methods, systems, and apparatus for a controller for a power circuit that interfaces distributed power generation with a power distribution grid, comprising: a first portion, including a maximum power point tracker, ...
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WO/2011/034861A1 |
A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a "delay time", thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of th...
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WO/2011/032183A1 |
Techniques are disclosed for eliminating or otherwise sufficiently suppressing spurious signals. The techniques are particularly useful in applications such as those that employ aggressor frequency sources along with a frequency conversi...
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WO/2011/030464A1 |
Provided is a PLL circuit (10) capable of rapidly performing frequency comparison in a control loop for switching between the voltage-frequency characteristic curves of a VCO (14). The PLL circuit includes a phase comparator (11) for ou...
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WO/2011/028348A2 |
Embodiments are described that compensate for a difference in a characteristic (e.g., of performance or operation) of a semiconductor device that is a function of the location of a die in a device. In one embodiment, a clock circuit may ...
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WO/2011/028157A1 |
The invention relates to a high-speed non-integer frequency divider circuit for use in generating frequencies in a communication device, comprising: at least four bi-stable memory devices each having an input terminal, a clock terminal a...
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WO/2011/027155A1 |
A clock device which utilises a reference signal of cyclic waveform having a reference frequency to produce an output frequency, wherein the output frequency is greater than the reference frequency, the clock device including: a variable...
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WO/2011/028248A2 |
Systems and methods for providing self-healing integrated circuits. The method is characterized in that the behavior of a circuit or a device in response to an input signal is observed. One or more operational parameters or characteristi...
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WO/2011/023030A1 |
An integrated circuit is disclosed in present invention, which includes: a first frequency division unit, a counter, an oscillation signal generation circuit and a second frequency division unit; wherein: the first frequency division uni...
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WO/2011/025341A2 |
Disclosed is a clock and data recovery circuit. The clock and data recovery circuit according to one embodiment of the present invention uses a hybrid phase detector which is composed of a linear phase detector and a binary phase detecto...
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WO/2011/024212A1 |
A first mixer (21) generates a first clock signal and a second clock signal having a phase opposite to that of the first clock signal according to a first control signal. A second mixer (22) generates a third clock signal having a phase ...
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WO/2011/018874A1 |
Equipped with a modulation unit that comprises a feedback circuit, which performs feedback control on an output signal from a voltage-controlled oscillator that is based on an inputted modulation signal, and a feed-forward circuit, which...
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WO/2011/016647A2 |
The present invention relates to a technique for designing a spread-spectrum clock generator. Instead of using a general sigma-delta frequency synthesizer or an analog frequency modulation system, the spread-spectrum clock generator of t...
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WO/2011/013485A1 |
Provided is a receiving unit, etc., using a voltage control type oscillator, wherein, without increasing capacitative elements for temperature compensation, a frequency property of the voltage control type oscillator by the temperature c...
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WO/2011/010581A1 |
A clock data restoration device (1A) is provided with a sampler unit (11), a phase comparison unit (12), a driving unit (13), a charge pump (14), a capacitative element (15), a potential adjustment unit (16), and a voltage control oscill...
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WO/2011/008999A1 |
A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clock...
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WO/2011/009001A2 |
A method for reducing average current consumption in a local oscillator (LO) path is disclosed. An LO signal is received at a master frequency divider and a slave frequency divider. Output from the master frequency divider is mixed with ...
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WO/2011/004580A1 |
Disclosed is a clock data recovery unit wherein the time required for clock data recovery is reduced. The clock data recovery circuit comprises: a multiphase clock generation circuit which generates a multiphase clock comprising a plural...
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WO/2011/003328A1 |
A global positioning system (GPS) receiver provided by the present invention includes a radio frequency converter for converting a GPS radio frequency signal to an analog GPS intermediate frequency signal; an analog-to-digital converter ...
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WO/2011/002941A1 |
A circuit for a voltage controlled oscillator (VCO) buffer is described. The circuit includes a first capacitor connected to an input of the VCO buffer that is connected to a VCO core. The circuit also includes a second capacitor connect...
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WO/2011/002944A1 |
A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digit...
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WO/2011/003040A1 |
A local oscillator communicates a signal of relatively low frequency across an integrated circuit to the location of a mixer. Near the mixer, a frequency-multiplying SubHarmonically Injection-Locked Oscillator (SHILO) receives the signal...
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WO/2011/001497A1 |
A PLL circuit (1) includes: a storage unit (70) which stores a control voltage in a desired frequency when a referencing signal is synchronized with a referenced signal; a current generation circuit (30) having a push-out circuit (31) wh...
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WO/2011/001652A1 |
In an ADPLL circuit (100), a DCO gain estimation unit (20) estimates, on the basis of the gain of a digital control oscillator (10), which is estimated in the state in which the loop gain with some value is set for a loop filter (18), an...
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WO/2010/151408A1 |
Devices and methods for varying individual periods or cycle times of upconverted clock signals within a corresponding reference clock cycle are disclosed. In some embodiments, these varying cycle times may improve signal synchronization ...
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WO/2010/151800A2 |
A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (Td), such that Td=kTVCO, where TVCO is the period of the synthesizer output signal. The method further incl...
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WO/2010/150311A1 |
Disclosed is a TDC circuit comprising: a first delaying circuit in which an even number of first inverting delay elements are connected in a loop; a second delaying circuit in which an even number of second inverting delay elements are c...
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WO/2010/150443A1 |
A voltage-controlled oscillator (11) produces an oscillation clock (CKout), and includes an inductor (100), a fine-control capacitor (101p), and a coarse-control capacitor (102p). A frequency divider (12) divides the oscillation clock (C...
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WO/2010/145836A1 |
An integrator (100) comprises an amplification and phase shifting element (170) with a feedback path (130) forming a loop and comprising a capacitive element (140). An input signal is summed into the loop, and the loop is arranged to osc...
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