| Document |
Document Title |
|
WO/2013/168325A1 |
A phase frequency detector realizes a highly linear conversion from noise-shaped ΣΔ modulation into charge quantities without degradation of phase locked loop (PLL) phase noise. The phase frequency detector may feature a construction o...
|
|
WO/2013/169071A1 |
A transceiver may include a reception (Rx) radio frequency (RF) part configured to process a received signal, a transmission (Tx) RF part configured to process a transmitted signal, and a phase lock loop (PLL) configured to provide a rec...
|
|
WO/2013/167196A1 |
The present invention relates to a method for generating a digital signal of tunable frequency, the method comprising: generating a periodic first analog signal, determining a sign of a first difference between a value of the first analo...
|
|
WO/2013/166447A1 |
A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include a digital control circuit configured to control the clock and data recovery circuit. The digital control circ...
|
|
WO/2013/162557A1 |
Apparatuses and methods for a self-biased delay locked loop with delay linearization are provided. One example delay locked loop (DLL) circuit (100, 200) can include a digital-to-analog converter (DAC) (104, 204, 304) and a bias generato...
|
|
WO/2013/159465A1 |
A multiple core processor device and a clock control implementing method therefor. The method comprises: each first type core processor running multiple sets of software systems employing one single phase-locked loop module, performing d...
|
|
WO/2013/162642A1 |
Plasma distribution is controlled in a plasma reactor by controlling the phase difference between opposing RF electrodes,, in accordance with a desired or user-selected phase difference, by a phase-lock feedback control loop.
|
|
WO/2013/158106A1 |
A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error s...
|
|
WO/2013/154585A1 |
Methods and systems to control an output frequency relative to a reference frequency. A frequency control system includes a dual-input bias generator to separately receive management and operational controls. The bias generator includes ...
|
|
WO/2013/155259A1 |
Aspects of the disclosure provide a local oscillator (LO) circuit that includes a first phase locked loop (PLL) circuit and a second PLL. The first PLL circuit is configured to generate a first oscillation signal having a first frequency...
|
|
WO/2013/154543A1 |
A re-circulating time-to-digital converter (TDC) can include a triggered reference ring oscillator (TRRO) and a delay module. The triggered reference ring oscillator can, when triggered by a reference signal edge, generate a periodic rin...
|
|
WO/2013/149636A1 |
The present invention relates to a device for compensating temperature drift of a voltage controlled oscillator (VCO) in a phased locked loop (PLL), said voltage controlled oscillator (VCO) having at least one varactor arranged for contr...
|
|
WO/2013/150013A1 |
The present invention relates to a device for controlling a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS) including a feedback loop having: a means (130) for digitizing at least one analog signal from said...
|
|
WO/2013/147839A1 |
An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a...
|
|
WO/2013/143237A1 |
A coherent bi-color light source device comprises an array substrate (10), a first laser tube (11) driven by a direct current signal (I1) and a second laser tube (12) driven by a modulation signal (I2) obtained by coupling a microwave si...
|
|
WO/2013/147861A1 |
According to some embodiments, a method and apparatus are provided to vary a clock signal frequency for a first time period between a lower limit of a range of problematic frequencies and a frequency lower than the lower limit, and vary ...
|
|
WO/2013/140755A1 |
An injection-locked frequency divider (ILFD) control unit (520) establishes a control parameter of an IFLD (303b) on the basis of the frequencies of a reference signal and of a frequency-divided signal measured in accordance with a contr...
|
|
WO/2013/141863A1 |
Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one ...
|
|
WO/2013/141837A1 |
Described herein is a self-biased oscillator. The self-biased oscillator comprises a first differentiator with adjustable resistance or capacitance, the first differentiator having an output node and an input node; and a second different...
|
|
WO/2013/136766A1 |
In this voltage controlled oscillator wherein oscillation frequency can be adjusted using a capacitor array, drift of carrier frequency is reduced in the cases where oscillation signals are frequency modulated after cutting the control l...
|
|
WO/2013/137863A1 |
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise ...
|
|
WO/2013/133933A1 |
An electronic device may contain clock circuits, transmitters, and other circuits that serve as sources of noise signals. The noise signals may be characterized by a noise spectrum. The noise spectrum produced by a noise source can be ad...
|
|
WO/2013/130671A1 |
Exemplary embodiments are directed to baseband beamforming. A device (150) may include a plurality of inputs for receiving differential in-phase (vip, vin)and quadrature data (vqp, vqn). The device may further include a plurality of swit...
|
|
WO/2013/130042A1 |
Apparatuses, systems, and methods are directed to maintaining optimal carrier tracking performance in view of operating conditions that prevail. Such configurations employ a phase lock loop that configured to generate an estimated phase ...
|
|
WO/2013/131027A1 |
An output portion of a charge pump receives control signals from a phase frequency detector and in response outputs positive current pulses and negative current pulses to a loop filter. A current control portion of the charge pump contro...
|
|
WO/2013/120334A1 |
A physical system device for a chip CPT atomic clock; linearly polarized circular divergent light (12a) emitted by a vertical-cavity surface-emitting laser (VCSEL) device sequentially passes through a first polarization beam splitter (6a...
|
|
WO/2013/121149A1 |
According to this method, a carry generation command (M) is applied repetitively to a command input (G) of a carry-propagation logic circuit (1), the application of said command (M) to said input (G) is timed by means of a reference cloc...
|
|
WO/2013/123427A1 |
Clock and data recovery (CDR) circuits and resettable voltage controlled oscillators (VCOs) are disclosed. In one embodiment, the CDR circuit includes a sampler configured to receive a data stream in a data path and sample the data strea...
|
|
WO/2013/115518A1 |
A variable capacitor is provided. The variable capacitor includes a plurality of capacitor segments. The plurality of capacitor segments are connected in parallel within the variable capacitor. When a plurality of candidate capacitances ...
|
|
WO/2013/112763A1 |
A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include...
|
|
WO/2013/109896A1 |
A frequency synthesizer circuit is disclosed. The frequency synthesizer circuit includes a phase and frequency detector. The frequency synthesizer circuit also includes a first charge pump and a second charge pump, each coupled to the ph...
|
|
WO/2013/101548A1 |
A method and apparatus for synchronizing a delay line to a reference clock includes a delay line that receives a clock input signal based on a reference clock and outputs a delay edge signal according to a control adjustment. An injector...
|
|
WO/2013/101159A1 |
An apparatus, system, and method, the method including receiving clock frequency parameter information for at least one clock source; receiving radio parameter information for at least one radio receiver; determining one or more spread s...
|
|
WO/2013/101231A1 |
A loop filter is described. The loop filter has first and second inputs and an output. A loop filter capacitor is coupled to the loop filter output. Sample switches are coupled to the second loop filter input. A voltage divider is couple...
|
|
WO/2013/101609A1 |
An RF power-supply (30) for driving a carbon dioxide CO2 gas- discharge laser (28) includes a plurality of power-oscillators (32) phase-locked to a common reference oscillator (11). Outputs of the phase-locked power-oscillators (32) are ...
|
|
WO/2013/102159A1 |
Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regen...
|
|
WO/2013/102160A1 |
Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regen...
|
|
WO/2013/095431A1 |
Described herein is an apparatus, method and system corresponding to relate to a low power digital phase interpolator (PI). The apparatus comprises: a digital mixer unit to generate phase signals from a series of input signals, the phase...
|
|
WO/2013/095549A1 |
Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A l...
|
|
WO/2013/095390A1 |
Apparatuses, systems, and a method for providing a PLL architecture with scalable power are described. In one embodiment, a system includes one or more processing units having a voltage regulator to generate a controllably adjustable sup...
|
|
WO/2013/094459A1 |
[Problem] To provide a DDS that achieves a more compact size and lower cost by not being provided with a ROM for storing a table or the like and by also minimizing the amount of computation. [Solution] A DDS (32) is provided with an NCO ...
|
|
WO/2013/095487A1 |
Pulse width modulation (PWM) based on selectable phases of a system clock may be implemented with respect to leading-edge-modulation (LEM), trailing-edge-modulation (TEM), and/or dual-edge-modulation. An initial pulse may be generated ba...
|
|
WO/2013/085971A1 |
Injection locked dividers provide a divided clock signal after being driven by a injected clock signal that is a multiple of the divided clock signal. At injected clock signal at 60 GHz generates a differential 30 GHz clock signal. One i...
|
|
WO/2013/083376A1 |
An analog phase-locked loop, PLL, (100, 200) is disclosed, comprising a voltage controlled oscillator (102, 202); a frequency divider (104, 204) having its input connected to an output of the VCO; a first phase detector (106, 206) arrang...
|
|
WO/2013/079685A1 |
The invention relates to a frequency synthesis device (100) comprising at least: first means (102, 104, 106, 108, 110, 112) capable of generating a periodic signal of frequency f 1 ; second and third means (114, 116) coupled to the first...
|
|
WO/2012/062207A9 |
A standard frequency and time adjusting method based on a rubidium oscillator. After a rubidium atomic oscillator is chosen as a reference frequency source, a field programmable gate array (FPGA) performs frequency doubling and frequency...
|
|
WO/2013/079389A1 |
A technique for cancelling or reducing crosstalk signals between controlled oscillators in an integrated circuit is provided. The technique involves an arrangement adapted to reduce a crosstalk signal generated by a first controlled osci...
|
|
WO/2013/082193A1 |
An apparatus for dividing a frequency by 1.5 to produce a quadrature signal is disclosed. The apparatus includes a divider that receives a differential input signal with a first frequency and two phases and creates a six-phase signal at ...
|
|
WO/2013/081176A1 |
Disclosed is a surface-emitting laser element including a semiconductor substrate and plural surface-emitting lasers configured to emit light with mutually different wavelengths, each surface-emitting laser including a lower Bragg reflec...
|
|
WO/2013/078108A2 |
Precision measurement of a period(s) of an embedded clock oscillator using a charge time measurement unit (CTMU) maintains a desired frequency accuracy of the embedded clock oscillator over a range of time, temperature and operating cond...
|
