PURPOSE: To avoid the generation of a crystal defect often viewed after forming an element by selecting the direction of the sidewall of a capacitance groove and the direction of the pattern of the element in the direction equivalent to <100>.

CONSTITUTION: The boundaries of element regions 1 and field oxide regions 3 for isolating the element regions 1 and the direction of the boundaries, the direction of the patterns of the elements, are selected in the direction equivalent to <100>. The directions vertical to the sidewall surfaces of capacitance grooves 2 are also directed in the direction equivalent to <100>. A wafer in which a P-type silicon layer 4 having 2μm thickness and 10Ω.cm resistivity is shaped onto a boron-doped (100)P++ type silicon substrate 5 having 0.005Ω.cm resistivity and an orientation flat in the direction equivalent to <100> is prepared, thus forming a desired storage element. Accordingly, no crystal defect is generated on the interface of the P-type silicon layer 4 and the P++ type silicon substrate 5, thus also lengthening the memory holding time.