Title:
METHOD FOR PLATING SEMICONDUCTOR SUBSTRATE
Document Type and Number:
Japanese Patent JP3820329
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To form a uniform seed layer by electroless plating by forming the seed layer on at least part of a barrier layer, which is inactive to electroless plating reactions by vapor phase growth.
SOLUTION: A method for plating semiconductor substrate is composed of a step of forming recessed sections on the surface of a dielectric layer 2 formed on a semiconductor substrate 1, and a step of forming a first conductive layer on the surfaced of the dielectric layer to cover the surface of the dielectric layer 2, including the recessed sections formed on the surface. The method is also composed of a step of forming a second conductive layer 6 on the surface of the first conductive layer 5 containing at least part of the surface of the layer 5, and a step of forming a plated metallic layer 6 on the surfaces of the first and second conductive layers 5 and 6 by electroless plating.
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Inventors:
Toshio Hataba
Takeyuki Itabashi
Haruo Akahoshi
Takeyuki Itabashi
Haruo Akahoshi
Application Number:
JP26041599A
Publication Date:
September 13, 2006
Filing Date:
September 14, 1999
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L23/52; C23C18/18; C23C18/52; H01L21/288; H01L21/3205; H01L21/768; (IPC1-7): H01L21/3205; C23C18/18; C23C18/52; H01L21/288; H01L21/768
Domestic Patent References:
| JP11204524A | ||||
| JP2000058645A | ||||
| JP2000058639A | ||||
| JP7321111A | ||||
| JP6029246A | ||||
| JP8083796A | ||||
| JP7283219A |
Attorney, Agent or Firm:
Kenjiro Take
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