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JP4724506B2 |
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JP2011135297A |
To improve the maximum operating frequency by reducing power consumption in a flip-flop circuit.A first data holding circuit (18) of a master-side element (100) and a second data holding circuit (19) of a slave-side element (200), are co...
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JP4717233B2 |
A single-phase clock CLK0 is divided into a clock signal CLK1 to drive nMOS transistor and a clock signal CLK2 to drive pMOS transistor, and the resulting clock signals are inputted to DFF circuits 1 to 3 constituting a frequency dividin...
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JP4719843B2 |
A frequency divider comprising a first flip-flop (M1, M2, M3, M4) having a first clock input (CI) for receiving a clock signal, the flip-flop further comprising a first set input (Q4) and a first non-inverted output (Q1). The frequency d...
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JP4713050B2 |
A phase-locked loop has a phase detector that generates a phase difference signal, a circuit that generates a phase-locked loop output signal having a frequency that is a function of the phase difference signal, a frequency divider that ...
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JP4702718B2 |
The frequency divider for high-frequency clock signal comprises: a shift register ( 8 ) having cells ( 10 - 13 ) for storing each bit of an initial word, said cells being series connected in a loop ( 14 ), and said shift register being c...
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JP4684919B2 |
Disclosed is an SSC controller that exercises control to supply a control signal to a phase interpolator which receives an input clock signal and varies the phase of an output clock signal in accordance with the control signal, and to fr...
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JP4672584B2 |
A system and method for configuring a phased-lock loop (PLL) dividing ratio which does not require the phased-lock loop circuit to lock. In one embodiment, the method includes inducing a substantially minimum or a substantially maximum f...
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JP4668430B2 |
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JP4668591B2 |
The object of the present invention is to provide a counter circuit, which can be operated with a high frequency clock. In order to realize the operation with a high frequency the counter circuit comprises first counter circuit 1 and sec...
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JP2011071732A |
To provide an integrated circuit device which can reduce delay time of serial data.The integrated circuit device 10 includes a shift register 18 which includes first to Nth (N is an integer of 2 or larger) registers 121, ..., 12N, is inp...
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JP4666462B2 |
A counter circuit includes a counter section having flip-flops of a plurality of stages. The flip-flops from a first stage to an (N-1)th (N is an integer more than 2) stage synchronously count a clock signal. A mask circuit section contr...
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JP2011066618A |
To provide an easy-to-handle counter circuit as digital logic circuitry, wherein the mounting area of the circuit is reduced, and also to provide a counting method.The counter circuit alternately connects: a plurality of flip-flop circui...
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JPWO2009050854A1 |
It has a first transistor on the high side power supply side and a second transistor on the low side power supply side, with collectors and emitters connected in series between the high side power supply and the low side power supply, an...
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JP2011040934A |
To provide a frequency divider circuit capable of correctly generating a frequency division signal of high frequency-division accuracy even for a high-speed clock signal.Variable integer frequency dividers (1A, 1B) capable of performing ...
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JP4632920B2 |
Provided is a method of changing an output current value of an off-chip driver by means of a counting circuit including pluralities of fuses for controlling the off-chip driver, that includes measuring the output current value of the off...
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JP2011024199A |
To provide a frequency divider capable of reducing current consumption while ensuring a performance as a frequency divider.Frequency divider circuits 10, 30, 50 are connected in series and in order to reduce current consumption of an ent...
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JP4624431B2 |
A data register (300) for use in a computer comprises a clock terminal (310) configured to receive a clock signal. A plurality of registers (320) are configured to selectively store data. A data input circuit (330) is coupled to the regi...
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JP4617840B2 |
A bootstrap circuit includes an output transistor, a bootstrap capacitor provided between the gate and source of the output transistor, a power source, and a circuit that performs ON/OFF control of a supply from the power source to the g...
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JP2011003174A |
To provide a power-saving trigger-type control device for instantly adjusting frequency, and a method thereof.The device includes a signal control unit having at least two signal input terminals, a counting control unit, and a clock gene...
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JP2010273044A |
To provide a frequency-divider circuit capable of balancing improvement of stability of circuit operation with reduction of power consumption, and to provide a semiconductor device.This frequency-divider circuit: includes an FF circuit 1...
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JP4589987B2 |
As shown in FIG.7, a visual device(2) detects position, size and form of at least one object in a digital image (111), by using a geometrical analysis means (37). In addition, the visual device (2) detects position, size, inclination, pa...
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JP4589253B2 |
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JP4592179B2 |
A delay locked loop (DLL) employs a gray code (an alternate code) counter as a delay register. Preventing a carry from arising at more than one bit can minimize skipping of delay time (discontinuous skipping thereof) if a metastable stat...
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JP4588786B2 |
A first frequency dividing circuit and a second frequency dividing circuit are provided, and these circuits frequency-divide two-phase external clocks injected from an external part, to output four-phase clocks with phase guarantee. Each...
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JP4589562B2 |
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JP4587620B2 |
A PLL circuit includes phase comparator (103) having a first input terminal to which a reference clock is applied; charge pump (104) generating a voltage conforming to a phase difference output from the phase comparator; loop filter (105...
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JP4583933B2 |
A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage ther...
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JP2010258642A |
To solve the problem of a conventional prescaler circuit that cannot perform high-accuracy frequency division at a high-speed operation.A prescaler circuit includes: an FF circuit 4 including a master-side latch circuit that generates an...
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JP2010258761A |
To obtain an output clock signal by frequency-dividing an input clock signal in a frequency dividing ratio, that is represented with optional rational numbers, by enabling an output clock signal to rise in falling of the input clock sign...
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JP4560039B2 |
A divide-by-n process is effected via a scale-by-four/n process followed by a divide-by-four process. A quadrature input clock facilitates a scale-by-four/n process, via a clock-phase selection process. By incorporating a terminal divide...
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JP4556730B2 |
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JP2010192625A |
To provide a semiconductor device which enhances the stability of circuit operation and enables reduction in power consumption.The semiconductor device is provided with a frequency-dividing circuit which has floating body type PD-SOI-MOS...
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JP2010192019A |
To provide a shift register changing the order of scanning signal lines while suppressing increase in circuit area or increase in current consumption.Each stage constituting the shift register includes: a thin-film transistor TS for incr...
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JP4533599B2 |
A clock divider in a DLL circuit for generating an internal clock signal synchronized with an external clock signal includes; a first clock dividing circuit for generating a first signal clock by dividing an input clock signal having a s...
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JP4536007B2 |
A semiconductor integrated circuit device ( 1 ) includes: a transistor switch (SWA) for electrically connecting and disconnecting output of a flip-flop (FF 64 ) of a shift register (SR 1 ) and input of a flip-flop (FF 65 ) of a shift reg...
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JP2010187356A |
To provide a frequency divider circuit capable of suppressing generation of a signal of an unwanted frequency.The frequency divider circuit includes: a shift register capable of storing at least n-bit data configured to shift an input si...
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JP4497708B2 |
A reset circuit outputting a reset signal /RESET when detecting an abnormal state in a ring counter is provided. The reset circuit divides the outputs of flip-flops constituting the ring counter into two groups, and check if either of th...
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JP4499009B2 |
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JP4494227B2 |
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JP2010130283A |
To provide a counter circuit capable of switching delay time by easy circuit structure. The counter circuit is constituted of flip-flops of a plurality of stages, to the initial stage of which a clock is supplied from an oscillator and t...
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JP2010124228A |
To maintain the high speed of selecting circuit operation regardless of the increase of a frequency division ratio. A fixed value of a fixed period according to a frequency division ratio is output from a decoder 3 to respective precedin...
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JP2010118981A |
To change a counter that counts signals to be counted, without changing wiring of signals to be counted to a count input circuit, or to supply signals to be counted to be supplied to one counter input circuit to a plurality of counters i...
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JP4452063B2 |
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JP4448128B2 |
A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further...
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JP2010074637A |
To provide a reliable up/down counter with a simple circuitry without using an external clock.The up/down counter device 10 outputs an up/down state signal (C) from two-phase pulse signals (A), (B) input to an up/down decoder 12 and gene...
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JP4442425B2 |
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JP2010056888A |
To provide a synchronization control circuit capable of further reducing an area or power consumption in comparison with conventional circuits.In a frequency divider circuit unit 26, a frequency-divided clock RSELO is generated by freque...
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JP4431134B2 |
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JP4425062B2 |
To solve the problem wherein it is not possible to read/write at high speed, because the conventional DRAM latches the line address and the column address by DFF and the address decoding is conducted a fixed time later, after the clock s...
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