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WO/1984/003406A1 |
An I2L non-integer programmable counter that has a high frequency precision that uses feedback to adjust count length. A first divider (12) adapted to receive a clock signal (FCL) having a first frequency and an input signal, provide a s...
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WO/1983/003502A1 |
The design of a system is simplified by making control lines from a microprocessor as small as possible when the frequency-dividing ratio of a programmable divider of a phase-locked loop is controlled by an up/down counter. This circuit ...
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WO/1982/003477A1 |
A frequency synthesized transceiver capable of tuning to a plurality of communication channels. The transceiver includes a receiver section (72) and a transmitter section (74) which are coupled to the synthesizer which generates the appr...
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WO/1982/002464A1 |
A clock rate generator which can be programmed to provide an output clock that is N/M times the rate of a standard clock where N and M are integers. The generator comprises a counter (20), a programmable memory (30), reset logic (40) and...
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WO/1981/002372A1 |
A high frequency divider suitable for use in a frequency synthesizer using a dual modulus prescaler (10) and two counters (30, 40) to achieve high speed and low current drain. The input signal is alternately divided by one of the two mod...
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WO/1981/002371A1 |
An improved frequency synthesizer suitable for use in mobile and portable radio applications using multiple dual modulus prescalers to achieve high frequency operation and low current drain. A first high speed prescaler (132) of limited ...
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WO/1981/002080A1 |
A logic circuit (20) is provided for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. Logic circuit (20) includes a voltage supply (V). A precharge trans...
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WO/1981/000472A1 |
An increment/ decrement circuit which is implemented using CMOS transistors. The circuit has a minimum of interconnect lines to an adjoining increment/ decrement circuit and also uses a reduced number of transistors. The increment/ decre...
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JP2024515147A |
Synchronous divider circuit with time-synchronized output. The synchronous divider circuit includes a plurality of divider stages each having a D flip-flop circuit and a respective retiming flip-flop circuit, wherein the output terminal ...
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JP2023149275A |
To provide a frequency divider and a control method for the same capable of stable operation even at high-speed operation.The frequency divider is configured with a plurality of flip-flops. The frequency divider includes a frequency divi...
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JP2023139097A |
To provide a double data rate (DDR) circuit and a data generation method for implementing precise duty cycle control.In a DDR circuit, a clock generator is configured to receive a source clock signal CKs to generate a pair of complementa...
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JP7350768B2 |
The power of a semiconductor device is reduced. The semiconductor device includes a latch circuit composed of a dynamic circuit. The latch circuit includes a first circuit having a decoding function, a plurality of capacitors, a pluralit...
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JP7324013B2 |
A fractional frequency divider comprises: a fractional frequency divider circuit configured to, by using an integer frequency division signal obtained by dividing an input signal by an integer frequency division ratio, generate a fractio...
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JP2023514844A |
The present application relates to a frequency divider and an electronic device, the frequency divider outputs a first level setting value as a frequency dividing ratio setting value in response to a second signal in the frequency dividi...
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JP7144696B2 |
A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, a...
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JP7141841B2 |
To provide a frequency divider input circuit and a PLL circuit capable of avoiding a decrease in an input amplitude into a frequency divider even when a VCO output is a high frequency, and capable of shutting down noise into a VCO from a...
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JP7132554B2 |
A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be ch...
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JP7108219B2 |
A frequency division correction circuit includes: a first frequency divider (302) configured to perform decimal frequency division (divide by 1.5) on an input signal and output a first frequency division signal (CK11) and a second freque...
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JP2022083858A |
To provide a multi-bit gray code generation circuit capable of outputting a gray code at a high frequency.A Bit2 gray code generation circuit (4) is constituted by a plurality of flip-flop circuits (41-44). Outputs of the flip-flop circu...
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JP2022078766A |
To provide a semiconductor device and a watch that can achieve an improvement in operation stability and prevention of an increase in power consumption, and can prevent an increase in manufacturing cost.A semiconductor device comprises: ...
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JP6985579B2 |
A frequency division correction circuit includes: a first frequency divider (302) configured to perform decimal frequency division (divide by 1.5) on an input signal and output a first frequency division signal (CK11) and a second freque...
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JP6972604B2 |
To provide a counter circuit, a measuring device, and a physical quantity sensor, capable of reducing a through current when a carry-over occurs and which can make the circuit configuration simple and small scale.The counter circuit incl...
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JP6966832B2 |
To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the...
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JP2021093632A |
To provide a divider circuit which can reduce the circuit scale.A divider circuit includes a plurality of D flip-flops connected in series, and from among the plurality of D flip-flops, a D flip-flop on the most input side of the divider...
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JP2021069112A |
To provide a counter capable of complement calculation and an image sensor including the same.An image sensor according an embodiment of the present invention includes a pixel sensor, a sampling unit, and a counter. The counter includes ...
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JP2021034784A |
To provide an injection synchronous frequency divider with a small circuit area and power consumption, large frequency division ratio, and a wide locking range.An injection-synchronous frequency divider 10 that generates a signal by divi...
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JP6831922B2 |
A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The...
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JP6823268B2 |
A demultiplexer circuit comprises: a first demultiplexing circuit (105) configured to convert a first input signal (IDT 0,1) having a first bit width (2) into a first intermediate signal having a second bit width (4) larger than the firs...
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JP6777292B2 |
To realize reduction of circuit scale and shortening of free run frequency correction time.A PLL circuit including a phase comparator 1, a charge pump circuit 2, a lowpass filter 3, a VCO4, an injection synchronous VCO6, an injection syn...
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JP6775640B2 |
To reduce a variation in gray code output timing between circuit blocks.The gray code counter includes a plurality of circuit blocks (11, 12, 13) for outputting gray codes (D1, D2, D3). The circuit blocks include: a gray code generation ...
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JP2020144968A |
To provide a novel shift register.The shift register includes a transistor 101, a transistor 102, a transistor 103, and a transistor 104. A first terminal of the transistor 101 is connected to a wire 111, and a second terminal of the tra...
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JP6746717B2 |
In some aspects, a local oscillator includes a voltage controlled oscillator, a multi-stage frequency divider including first and second stages, and a duty-cycle converter. An output node of the voltage controlled oscillator is coupled t...
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JP6732565B2 |
PURPOSE: To provide a radio communication device about which both reduction in circuit scale and reduction in power consumption are efficiently achieved.CONSTITUTION: A signal generation circuit includes: a PLL (Phase Locked Loop) synthe...
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JP6718668B2 |
An N-bit Gray counter, with N an integer greater than 1, comprises a string of N logic cells connected in cascade, wherein each logic cell comprises an input port for a succession of clock pulses, a circuit for generating a Gray count bi...
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JP6694836B2 |
To suppress a residual jitter when forming a strove while capable of using a fixed BPF for a passing frequency range.A trigger circuit 2 includes: a DDS 12 that outputs a trigger clock input within a movable frequency range at an arbitra...
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JP6684218B2 |
A plurality of latch circuits driven at rising of a clock signal and a plurality of latch circuits driven at falling of the clock signal are alternately connected, and generation circuit generates a plurality of frequency divided clock s...
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JP6686571B2 |
To provide a technology for integrating a synchronous counter circuit and an asynchronous counter circuit while suppressing an increase in circuit resources.A counter circuit 8 comprises: JK type flip flops FF in a plurality of stages; a...
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JP6663931B2 |
In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency ban...
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JP6655896B2 |
The present invention provides a frequency synthesizer that is switchable at a high speed and includes a few unnecessary frequency components in an output frequency signal. In a frequency synthesizer 1, a DDS 2 operates based on a clock ...
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JP2019220855A |
To provide a frequency dividing circuit that can change a frequency division ratio and can reduce current consumption.A frequency dividing circuit comprises: first to n-th (n is an integer of 4 or more) D-type flip flops that each have a...
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JP2019220856A |
To provide a frequency dividing circuit that can change a frequency division ratio and can reduce current consumption.A frequency dividing circuit comprises: a first frequency divider that, for an integer n of 1 or more and an integer m ...
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JP6561138B2 |
A circuit for a divider or counter may include a frequency divider having multiple rings for dividing an input frequency to obtain an output frequency. The first and second rings may include an odd-numbered plurality of elements, such as...
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JP6524540B2 |
A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a det...
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JP2019057281A |
To provide a clock generation circuit that can instantly generate a clock of a predetermined frequency.In a semiconductor device 100, a clock control module 10 includes a PLL circuit 1 and frequency dividers 2 and 3. The frequency divide...
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JP6482032B2 |
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JP6463169B2 |
An electronic circuit includes a generating circuit for generating a first group of signals and a second group of signals, and a transmission path for transmitting the first group of signals and the second group of signals. The first gro...
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JP6454619B2 |
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JP6437142B2 |
A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a ...
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JP2018164151A |
To provide a high-quality frequency divider circuit.A frequency divider circuit comprises: a first flip-flop having a first input end to which a clock signal is inputted as well as a second input end to which a first signal is inputted; ...
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JP2018528675A |
Methods and devices for synchronizing frequency dividers in different LO paths using pulse swallows. One exemplary device is generally from a first path having a first frequency divider configured to generate a first frequency divider fr...
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