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WO/2015/065543A1 |
An apparatus relates generally to serializer-deserializers. In such an apparatus, a first serializer-deserializer (210) has a first data path (251) and a data eye path (252). The first data path is coupled to a first data out interface (...
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WO/2014/208552A1 |
An objective of the present invention is to set an optimal phase with greater precision. A phase adjustment circuit (30) comprises: a phase shift clock generating unit (31) which generates a clock signal of an arbitrarily set phase; a co...
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WO/2014/074300A1 |
A serializer and de-serializer circuit which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scal...
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WO/2014/055204A1 |
A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder (290), at least one digital frequency mismatch number; decoding, with the at least one decoder (290), the at ...
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WO/2013/139033A1 |
A configurable media independent interface in an integrated circuit device includes a first plurality of channels and a second plurality of channels, wherein each channel of the first and second pluralities includes a transmit path. The ...
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WO/2013/109263A1 |
Embodiments of the invention describe an apparatus, system and method for executing self-correction logic for serial-to-parallel data converters. Embodiments of the invention receive one of a plurality of serial data streams from a perip...
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WO/2013/061565A1 |
A serial-to-parallel converter which includes n input latching elements, INL1, INL2,... INLn, configured to sample n successive data of a serial input data stream, respectively; k intermediate latching elements, IL1, IL2,... ILk, configu...
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WO/2013/030298A1 |
A de-serializer, such as forming part of a SERDES, in which a point in time of receipt, on the serial data path, of receipt of a particular part of a data packet, such as an SOF, is determined from when that part is output on the paralle...
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WO/2012/135458A1 |
Patterns detected by a low-speed receiver at the output of a high-speed multiplexer are used to determine when multiplexer input lanes are deskewed.
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WO/2012/134652A2 |
A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consu...
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WO/2012/082572A2 |
In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase co...
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WO/2012/083279A2 |
A serial-to-parallel converter includes a sampling unit that may, in response to a serial clock signal, sample a serial data stream and provide an even serial data stream, and an odd serial data stream. The serial-to-parallel converter a...
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WO/2012/073809A1 |
Provided is a method capable of serial transmission of data having varying data values in a constant short period while increase in power consumption is suppressed. A first data sequence conversion circuit (121) and a second data sequenc...
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WO/2012/055615A1 |
The invention relates to a method for transmitting digital data via a line, comprising steps of providing a clock signal and transmitting the digital data synchronously to the clock signal, wherein the clock signal comprises a frequency ...
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WO/2012/011292A1 |
In the present disclosures, by means of a control unit (21a), unit data that configures a digital data group is extracted as parallel data having 8-bit units and is output to a buffer (21c). Thereafter, by means of a process of unit data...
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WO/2011/150172A1 |
A method and apparatus to serialize parallel data input values is disclosed. In a particular embodiment, a method of serializing parallel data input values includes receiving multiple data input values in parallel at an input tier of a s...
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WO/2010/136995A1 |
The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of fr...
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WO/2010/131306A1 |
A data transmission unit (100) having a parallel/serial conversion function is supplied with a clock by a PLL circuit unit (200). In the PLL circuit unit (200), a first multi-phase clock to be given to a first parallel/serial conversion ...
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WO/2010/097876A1 |
A transmission unit (210) includes an insertion unit (21) which performs multiple insertion processing for inserting judgment information between each two adjacent line data of a plurality of consecutive line data included in serial imag...
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WO/2010/083371A1 |
According to one embodiment, a high speed serializer (100) for multiplexing 2 N data input (D00, D10, D01, D11), N being a positive integer, comprises one less than 2N multiplexing cells (130a, 130b, 130c) arranged in N stages (110,120)....
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WO/2010/067476A1 |
Provided is a testing apparatus for testing a device to be tested. The testing apparatus is provided with a serializer, which receives a parallel data of N bits (N is an integer of 2 or more), converts the parallel data into M pieces of...
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WO/2010/021164A1 |
A serializer (15) is equipped with a plurality of input terminals (15a, 15b) into which a plurality of binary signals are input in parallel, and converts the plurality of input binary signals into serial binary signals and transmits the ...
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WO/2009/158541A1 |
A deserializer circuit and method convert a serial bit stream into a parallel bit stream according to a parallel grouping. The deserializer and method include alternatingly demultiplexing a serial data stream into first and second bit st...
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WO/2009/155874A1 |
A parallel-serial converter is provided, and the parallel-serial converter comprises a low speed serializer module, a transmission module and a high speed serializer module. A parallel-serial conversion method is also provided, and the p...
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WO/2009/121186A1 |
A high-speed video serializer has an X bit parallel input bus and a Y bit parallel output bus, where X and Y are multiples of one another (e.g., 2). A multiplexer is connected between the input bus and the output bus and is operated such...
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WO/2009/121185A1 |
A method for converting data received in either a Level A or Level B SMPTE 425M compliant format into either a Level B or a Level A compliant format, respectively, includes receiving and processing data in one of a Level A or a Level B S...
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WO/2009/025794A2 |
A serializer is described that incorporates a register and a delay circuit for each serial bit. The serializer provides a timing signal that is generated and output simultaneously with the output of the data bit that ensures close timing...
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WO/2009/017386A2 |
A serializer/deserializer interfaces a microprocessor/controller with I/O devices over a flexible hinging cable. The I/O devices have parallel interfaces as does the controller but the serializer/deserializer reduces the number of signal...
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WO/2009/004263A1 |
The invention relates to a transition between different sub-band domains for compacting in a single processing operation the application of a first vector X(z), comprising a first number L of components in sub-bands, to a bank of synthes...
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WO2008070978A9 |
Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, du...
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WO/2008/104958A2 |
A data recovery circuit has a delay locked loop circuit (22) for providing clock recovery from an input and generating a multi-phase clock signal (44). This is used to sample input data. A phase locked loop circuit (24) generates an outp...
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WO/2008/105053A1 |
A data transmission circuit for converting a parallel data signal into a serial data signal for transmission comprises a clock generation circuit, an output circuit, and a shift register circuit in order to perform the data transmission/...
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WO/2008/067659A1 |
A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined...
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WO/2008/067652A1 |
A memory system architecture is provided in which a memory controller controls operations of memory devices in a serial interconnection configuration. The memory controller has an output serial interface for sending memory commands and a...
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WO/2008/067665A1 |
A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) is serially interconnected. Each device has device type information on its device type. A specific device type (DT) and ...
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WO/2008/064466A1 |
A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is d...
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WO/2008/064028A2 |
A Serializer/Deserializer (100; 400) apparatus comprises a serializer (100; 400) adapted to take N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter, a transmitter enable block (110, 120, 420) a...
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WO/2008/027586A2 |
A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mo...
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WO/2008/021749A1 |
A Double Data Rate (DDR) serial encoder is provided. In one aspect, the DDR serial encoder includes a non-glitchless multiplexer and digital logic for ensuring a glitch-free encoder output. By using a non-glitchless multiplexer, the size...
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WO/2008/008546A2 |
Universal reconfigurable scan architecture reconfigures scan structures via scan-load operation, thereby eliminating interconnect network distributing configuration signals, and employs common scan circuitry identical for designs at mask...
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WO/2007/144035A1 |
An apparatus (2) for parallel/serial conversion of a plurality of evaluation variables which are determined from detected signal variables by in each case one detector (131, 132, 133, 134, 135) comprises a first buffer store (18) for syn...
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WO/2007/109224A2 |
Embodiments include a serial interface circuit, serial interface method and an apparatus including a serial interface circuit. Embodiments of a serial interface circuit can include a frequency divider implemented by using a counter inste...
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WO/2007/071574A1 |
The field of the invention is that of interfaces for transmitting synchronous digital input signals composed of bits sent in series at a transmission frequency equal to a first integer multiple M of a first clock frequency. The interface...
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WO/2007/064785A2 |
In one embodiment, a pulsed signaling multiplexer is described that comprises a first AC-coupled transmitter (104a) and a second AC-coupled transmitter. (104b) The first AC-coupled transmitter (104a) includes a first driver having a firs...
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WO/2007/058708A1 |
In accordance with certain embodiments, an optical network terminal (ONT) is provided that comprises a processor module, a serializer module and an optical transmitter. The processor module may represent an FPGA device, while the seriali...
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WO/2007/037132A1 |
Provided is a parallel-serial conversion circuit, which can set a clock frequency and a data width flexibly. The parallel-serial conversion circuit (100) converts parallel data of a clock frequency (f) and (m x n) (m and n are natural nu...
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WO/2007/037864A1 |
A clock circuit for outputting serial data without using a PLL is described. The clock is a VCO designed to start at a frequency that is slightly higher than necessary to preserve the data. The frequency of the clock is measured and if t...
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WO/2007/033305A2 |
A system and method of transmitting and receiving bit serial information is disclosed. In a differential embodiment, serial bits are transmitted by a pair of line-matched differential drivers that are ac coupled to a two-conductor transm...
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WO/2007/027833A2 |
A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply nois...
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WO/2006/129579A1 |
A transmitting end device (10) includes memories (MT) for storing a plurality of previously transmitted signals, while a receiving end device (20) includes memories (MR) for storing a plurality of previously received signals. Comparators...
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