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WO/1991/015926A1 |
In a method of aligning a data receiver (2) with a data transmission from, e.g., a head-end station (1), data is encoded for transmission with a hybrid differential coding scheme including at least one invalid codeword, and the coding sc...
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WO/1990/010903A1 |
The serial data receiving circuit of the invention comprises a most significant bit input detecting circuit (20) which produces a predetermined control signal in synchronism with the reception of the most significant bit of serial data o...
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WO/1989/002683A1 |
A method in the reception of a group of information signals and a receiver for use in the performance of the method, where the information signals are transmitted serially and propagate in a receiver along a first energy propagation path...
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WO/1987/005454A1 |
A method and apparatus for conversion of a plurality of information signals from parallel to serial representation and vice versa. According to the invention the time delay introduced by the use of ordinary shift registers is obviated by...
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JP7332783B2 |
The present invention provides a SerDes interface circuit and a control device which make it possible to use the same SerDes to perform data transfer of different communication rates. The present invention includes: a FIFO that inputs a ...
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JP7269610B2 |
To provide a slave side device that connects, in M stages, clock-synchronized serial data receiving circuits that convert serial data of a reference bit number into parallel data, and performs conversion into parallel data of "reference ...
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JP7193110B2 |
A multi-lane serializer device 1 includes serializer circuits 101 to 10N and a controller 20. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnor...
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JP2022541831A |
A circuit arrangement for calibrating circuitry within an integrated circuit device is described. The circuit arrangement is a main circuit (1102) configured to receive input data at a first input (1106) and generate output data at a fir...
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JP7128694B2 |
To provide a monitoring device for a parallel-serial conversion circuit which can detect failures of the parallel-serial conversion circuit.There is provided the monitoring device for a parallel-serial conversion circuit 2, which convert...
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JP7053098B2 |
To allow setting of a test mode with an easy configuration instead of a precise configuration, and suppress increase of the number of terminals.There is provided a test mode setting circuit which gives N number of test mode signals to an...
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JP6880846B2 |
There is disclosed herein multiplexer circuitry. In particular, there is disclosed a latch circuit for use as a multiplexer to multiplex information carried by respective pairs of input information signals onto an output information sign...
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JP6866321B2 |
To provide a serial-parallel conversion device capable of performing processing with simple control.A serial-parallel conversion device includes a D/A conversion unit 1 that obtains analog data by performing processing opposite to repeti...
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JP6837549B2 |
A noise cancelling circuit includes: a first parallel-serial conversion circuit which converts inputted 2N-bit parallel data into serial data; an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in...
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JP6735095B2 |
To provide a signal multiplexing device capable of reducing power consumption by serializing one signal and selectively outputting any one of the one signal and the other signal.A signal multiplexing device 1 comprises prestage buffer pa...
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JP6701443B2 |
A signal processing circuit is provided that generates output signals to be output from spatially different output ports based on bit combinations of an input word consisting of a plurality of bit signals. A distributed memory, a ROM and...
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JP6699881B2 |
To provide a transmitter, a receiver and a transmission system capable of preventing generation of decoding error while reducing delay time in decoding processing.The transmitter in an embodiment, includes: a serial conversion processing...
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JP6687392B2 |
A serializer device (1) includes a first latch unit (11), a second latch unit (12), a conversion unit (13), a frequency division unit (14), a load signal generation unit (15), a phase difference detection unit (16), and a reset instructi...
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JP6657481B2 |
An SoC integrated circuit package is provided in which the analog components of a SerDes for an SoC die in the SoC integrated circuit package are segregated into a SerDes interface die in the SoC integrated circuit package.
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JP6631117B2 |
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JP6611993B2 |
A wiring aggregation apparatus includes at least one subunit. The subunit includes: an input/output module to output, to a control module, a first serial signal obtained by performing parallel-serial conversion on plural pieces of contac...
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JP6594652B2 |
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JP6575390B2 |
A parallel-serial conversion circuit including a data transmission unit to output first data and second data of a prescribed pattern in accordance with a second clock obtained by dividing a first clock, a first flip flop to receive the f...
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JP6503880B2 |
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JP2019036948A |
To provide circuitry of generating a voltage, and a method of operating a sensor system.The circuitry comprises: a sequence generator configured to provide a sequence of data words consisting of bits, where the number of bits is greater ...
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JP6467878B2 |
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JP6413585B2 |
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JP6370263B2 |
To provide a data transmission device and the like, capable of securing transmission quality without increasing transmission speed in performing serial transmission on digital data obtained by imaging a subject.A data transmission device...
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JP6357141B2 |
In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the ...
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JP6329777B2 |
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JP6239987B2 |
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JP6221603B2 |
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JP6221857B2 |
A phase adjustment circuit includes a comparator circuit and a synchronization circuit. The comparator circuit compares, with respect to each of multiple lanes, a common reference clock signal fed to each lane with first and second trans...
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JP6194049B1 |
[Subject] The delaying amount of an optical trigger pulse is adjusted without using a mechanical flexible region. [Means for Solution] An optical system is individually with optical-intensity-modulation part 103 which can be adjusted abo...
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JP2017519427A |
Disclosed are serializers and deserializers for odd ratio parallel data buses. In one embodiment, serializers and deserializers operating on an odd number of parallel data bits operate on a half-rate clock to provide a full clock rate se...
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JP6156589B2 |
A receiving circuit includes a deserializer circuit configured to convert serial data to parallel data in accordance with an operating clock, a phase difference detection circuit configured to detect a phase difference between the operat...
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JP2017103668A |
To make it possible to easily align phases of respective data after parallel conversion.A receiving circuit 100 comprises: an optical module 101 that converts input data to parallel data; a SerDes 102a that converts one piece of data of ...
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JP6133523B1 |
A system and a method for generating a clock phase signal which has exact timing relationship are indicated. For example, four clock signals estranged 90 degrees are generable from a differential CML clock signal. A CML/CMOS converter ch...
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JP6127807B2 |
A transmitting circuit includes: a multiplexer configured to output a third digital signal obtained by alternately synthesizing a first digital signal of a predetermined cycle length and a predetermined data rate with a second digital si...
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JP6126601B2 |
a circuit arrangement and a corresponding method are proposed, in which the power consumption required for the transfer of L[ow]P[ower] data is as low as possible.
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JP6126600B2 |
On the basis of single-ended signals based on logic levels, and of differential, in particular common-mode-based, signals, a circuit arrangement and a corresponding method are proposed, in which a serialized signal transmission is always...
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JP6126603B2 |
On the basis of single-ended signals based on logic levels, and of differential, in particular common-mode-based, signals, a circuit arrangement and a corresponding method are proposed, in which it is possible to further reduce the size ...
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JP6126604B2 |
On the basis of single-ended signals based on logic levels, and of differential, in particular common-mode-based, signals, a transmission arrangement and a corresponding method are proposed, in which a serialized signal transmission is a...
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JP2017033003A |
To provide a pixel unit of new structure.A pixel unit includes a first semiconductor layer of a first transistor 3502, a second semiconductor layer of a second transistor 3503, a first conductive layer 39a having an area functioning as a...
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JP6077097B2 |
A media independent interface in an integrated circuit device includes a first plurality of channels, each including a data transmit path and a data receive path, and a second plurality of channels, each including a transmit path to tran...
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JP6060637B2 |
A parallel-serial conversion circuit includes an adjustment circuit that receives a parallel input signal having a plurality of bits and generates and outputs a parallel output signal having a plurality of bits. A conversion circuit coup...
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JP2016165056A |
To provide a parallel-serial conversion circuit capable of ensuring sure bit conversion timing with the suppression of the increase of a consumption current and a circuit area.The parallel-serial conversion circuit includes: a 4-input 1-...
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JP5962322B2 |
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JP5937719B1 |
[Subject] Parallel/serial converter which can generate an outstanding serial electricity signal of high amplitude and a waveform is provided. [Means for Solution] Parallel/serial converter (1, 1A*1D) concerning the present invention, It ...
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JP5933899B2 |
A programmable logic device ('PLD') is augmented with programmable clock data recover ('CDR') circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PL...
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JP5922280B1 |
To obtain a conversion signal of NRZ by performing series / parallel conversion based on a selective push / pull scheme. A turn-on gate pulse gpon2 is input to a gate g of a charging transistor T2 to turn it on, and a control pulse cp is...
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