Title:
SENSE AMPLIFIER
Document Type and Number:
Japanese Patent JP2630289
Kind Code:
B2
Abstract:
PURPOSE: To prevent output of false data by using first and second differential amplifiers which amplify differentially the potential of a signal read out from a selected memory cell and a reference potential in reverse phase to each other and an equalizing circuit which executes equalization at a prescribed timing.
CONSTITUTION: The potential of an output signal AO of an amplifier circuit 2 during an equalization period is a voltage being equal substantially to the threshold voltage of an inverter circuit IV21. On the other hand, the inverter circuit IV21 and the inverter circuit IV31 of a latch circuit 3 are so designed and manufactured as to have the same threshold voltage. Accordingly, the voltage of the output signal AO of the amplifier circuit 2 during the equalization period and a threshold Viv of the inverter circuit IV31 become equal to each other. At the time when a control signal BC changes and the output signal AO changes to a high level, the voltage of the output signal AO changes from Viv to the high level simultaneously when the control signal BC changes at the time t7. Output data SDO of a sense amplifier are at a low level and no false data are outputted, and also, the operating speed does not lower.
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Inventors:
JINBO TOSHIKATSU
Application Number:
JP788195A
Publication Date:
July 16, 1997
Filing Date:
January 23, 1995
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G11C17/00; G11C7/06; G11C16/06; G11C16/28; (IPC1-7): G11C16/06
Domestic Patent References:
| JP8180693A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)