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JP3822681B2 |
To restore errorless data regardless of the existence of noise at the time of data reproducing from a recording medium. The transition of a quaternary code read out at the time of reproducing from the recording medium unequivocally deter...
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JP2006237930A |
To provide a judging method which is improved in precision in discriminating a Manchester code.The judging method comprises a measuring step (53) of measuring a time between a first fall by a first Manchester code and a following fall by...
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JP3817958B2 |
To obtain a PWM control circuit that can generate a PWM signal high in resolution with a small circuit scale and to obtain a microcomputer and an electronic device. This PWM control circuit is provided with a PWM period setting register ...
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JP3811873B2 |
To simply restore a signal that is received in variable rate in a correct symbol timing by interpolating, after calculating filter count for every sample cycle and performing signal processing of only effective data among outputs of an i...
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JP3810690B2 |
To reproduce multi-valued data more correctly than before. When binary data are converted into multi-valued data whose each symbol consists of (n) bits (n is an integer of ≥2) and test data including 2(Mxn) combinations of the multi-va...
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JP3810790B2 |
Methods and apparatus for encoding and decoding information in broadcast or recorded segments signals are described. In certain embodiments, an audience monitoring system encodes identification information x(w) in the audio signal portio...
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JP3811030B2 |
To acquire an output without unnaturalness in a listening sense even when receiving a signal with a relatively high peak level. The digital amplifier is provided with; a level detector 41 that detects a level of an input analog signal; a...
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JP3810703B2 |
To enable easier and correct reproduction of multi-valued data even in the case of such a recording density as high as such a good eye hight cannot be obtained. One symbol includes (n-1) bit data in n×m-1 (n and m being integers in n≥...
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JP2006203756A |
To provide a data processor, a data processing system and a data processing method with high effect of reduction of power consumption in the whole system.A register file part 31 outputs register file signals DX1, DXb in data restoration ...
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JP3800498B2 |
To minimize a pulse resting period to an ignorable degree without causing a pulse non-output state in the output of pulses of a number proportional to a measurement value in a fixed period. In this device, the value of the signal measure...
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JP3798430B2 |
A data transmission apparatus for transmitting an original data has a converter for converting the original data to sequential data codes. The data code is formed by a combination of HIGH level binary codes and LOW level binary codes. Th...
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JP2006516783A |
The present invention relates to a method of copy protecting optical discs, such as CDs or DVDs. Instead of encoding data onto the CD-ROMs in a conventional manner which ensures balanced dc content, for copy protection the digital data i...
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JP3793535B2 |
A method and apparatus of converting a series of data words into modulated signals generates for each data words, a number of intermediate sequences by combining mutually different digital words with a data word, scrambles the intermedia...
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JP3772264B2 |
To provide a coding method without loss by using the same address for the sub-sets of the same code word in different states. After receiving p-bit input blocks 310, an encoder converts the respective input blocks 310 to corresponding q-...
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JP3771859B2 |
To provide an optical information recording method and an optical information recording device, in which the setting method for recording power is improved in performing intensity modulation recording with a smaller number of pulses than...
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JP3769753B2 |
To perform encoding by using a code conversion table such that the parities of code sequences are up to the time point where the codes became identical are different. According to the codeword allocation in the code conversion table, the...
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JP2006085167A |
To provide a method of reducing required data to limit the requirements in terms of external memory and bandwidth.In a method and device for generating subfield codes for a picture displayed on a display device like a plasma display pane...
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JP2006086844A |
To reduce an error rate of decoding results by correctly decoding Manchester encoding data without being affected by waveform distortion due to the deviation of duty with a simple circuit structure.A phase synchronous circuit 1 generates...
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JP3760963B2 |
To provide a simple circuit constitution and to eliminate the need for the design of a new device by converting a code string in which a minimum run after a variable length code is converted continues for more than the prescribed number ...
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JP3760961B2 |
To stably reproduce a clock by dividing a data line at every m bits so as to correspond to a code word, making a minimum run a specified value or above, converting the data line of m bits to a fixed length code of n bits and limiting the...
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JP3757918B2 |
To provide a simple encoding modulation method and demodulation method having an encoding rate equivalent to (1, 7) modulation and suitable for high density recording with less DC components. In the encoding modulation method and a modul...
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JP3754080B2 |
A method of converting a series of m-bit information words to a modulated signal. For each information word from the series an n-bit code word is delivered. The delivered code words are converted to the modulated signal. The code words a...
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JP2006506773A |
An asynchronous transfer mode digital document delivery system is provided. A customer premise unit is configured to permit a customer to order and receive a data stream. A buffer is coupled to the customer premise unit to store the data...
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JP3747839B2 |
To provide a code conversion system in which 64B/65B conversion and inverse conversion can be performed with a little hardware resources by omitting redundant arithmetic. When a data/control flag 61 is '1', in a control code converting p...
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JP3748496B2 |
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JP3749281B2 |
PURPOSE: To constitute a data receiver of exclusive hardware with a relatively small number of parts. CONSTITUTION: A metric calculator 7 calculates a metric for a decoder 4 for each sample of a base band signal. The metric is a binary w...
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JP3744837B2 |
To provide a code modulation method that is immune to channel distortion and to provide a detection method that can correct a detection error in the case of detecting data produced by the modulation method. The modulation method of this ...
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JP3744824B2 |
A modulation method and a demodulation method for a run length limited (RLL) code having an improved direct current (DC) suppression capability are provided. In this modulation method, received data is modulated using a DC suppression co...
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JP3746232B2 |
A CMI coding method, a CMI decoding method, a CMI coding circuit, and a CMI decoding circuit which do not adversely affect a main signal to be CMI-coded and which allow a high-speed asynchronous signal to be always transmitted by Coding ...
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JP2006031757A |
To provide a demodulator in which an error rate can be reduced in signal reproducing processing of an optical disk device.In this demodulator 1, a slice signal input to a slice signal input terminal IN is read, a data word is demodulated...
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JP2006503323A |
Coding of an audio signal (x) represented by a respective set of sampled signal values for each of a plurality of sequential segments is disclosed. The sampled signal values are analyzed ( 130 ) to generate one or more sinusoidal compone...
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JP2006501595A |
The present invention relates to a bit detection method for detecting the bit values of bits of a channel data stream stored on a record carrier, wherein the channel data stream resides on an N-dimensional lattice of bits and comprises a...
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JP3733115B2 |
A circuit for recovering a current sense signal which is offset by a common mode displacement, such is the case when the signal is the voltage across a current sense resistor located on the high side bus or between the switches of a moto...
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JP2005538489A |
A data recording, reproducing, detecting and/or evaluating apparatus includes a modulator which modulates input information data by a predetermined modulation method, according to a first clock signal having a basic clock period (T) for ...
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JP2005538632A |
A method for coding information in an electronic circuit and an electronic circuit for coding information uses at least two electrically coupled signal paths (X0, X1). Cross-talk between two electrically coupled signal paths (X0, X1) can...
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JP2005339792A |
To provide a method for converting a series of m-bit information words to a modulated signal.For each information word from the series, delivered code words are converted to the modulated signal. The code words are distributed over at le...
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JP3722331B2 |
To conduct DSV control with low redundancy. A DSV bit decision insert section 11 inserts a DSV-bit to a received data string. A modulation section 12 has a conversion table. Each of the element of the table is an element which is uniquel...
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JP3719367B2 |
To obtain a decoding device, capable of making a circuit scale smaller by simplifying the circuit configuration and reducing power consumption. This decoding device, which divides a signal recorded with pulse width modulation into two da...
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JP2005535056A |
An information storage medium (a disc) includes an area and a user data area. The area includes a recordable zone having a drive & disc zone in which information on a drive and information on a state of the disc are recorded. The drive &...
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JP3716421B2 |
To attain the stable reproduction of clocks. A constraint length decision part 12 stores a table which converts a variable length code having its basic length of (n) bits into the data having its basic length of (m) bits and decides the ...
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JP2005318593A |
To reformat binary image data on two or more flat surfaces.There are various exemplary embodiments, however, this system includes a segmenter to segment binary image data of text on a first flat surface. A subtracter subtracts a binary i...
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JP2005286773A |
To solve a problem that a digital signal detection circuit at a receiver side is made complicated in the case that a transmission side apparatus connected to a network system outputs a biphase modulation digital signal.An interface appar...
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JP3699380B2 |
To determine digital data stream coded by Run Length Limited (hereinafter RLL) swiftly and precisely so as to record data on a recording medium. The digital data modulating method includes the steps of: comparing a preset critical value ...
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JP3696812B2 |
To reduce power consumption by transmitting a huge amount data with a few number of signal lines in an input output interface that transmits/ receives a signal. The input output interface expresses logical values according to the sequenc...
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JP3695329B2 |
To provide a device and method for bus-encoding/decoding for a low power digital signal processor system using a narrow data bus. This device is provided with a conditional inverting means for inverting lower (n-1) bit data by bit units ...
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JP3687873B2 |
To provide a means to extract valid data from data of Manchester codes used for digital data transmission or the like. The data extract circuit is provided with a counter 3 that counts number of clock pulses by using input data of Manche...
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JP2005223669A |
To enable the mean value formation method of a value conversion means output to be built at low cost, and with a high accuracy and a high degree of freedom.As opposed to the input of a plurality of values, a method including a value conv...
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JP3683892B2 |
To provide a method and system for differential transmission of data on a bus overcoming the limitations of conventional systems. This differential transitional coding uses a differential bus. Use of differential transition includes a st...
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JP3682058B2 |
To establish a method for resetting a communication link between a base unit and a remote unit. The system includes the steps of continuing to count a second clock signal generated by a second means in the remote unit; synchronizing a se...
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JP2005523601A |
A signal includes a runlength limited (RLL) encoded binary d,k channel bitstream, parameter d defining a minimum number and k defining a maximum number of zeroes between any two ones of the bitstream, or vice versa. The signal further in...
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