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Patent Searching and Data


Matches 901 - 950 out of 39,241

Document Document Title
WO/2013/083190A1
The invention relates to a method (100) for recovering clock information from a received optical signal, the received optical signal having a first (x) and a second (y) principal state of polarization. The method comprises modifying (101...  
WO/2013/082812A1
Disclosed is a method for determining a master clock device, comprising receiving a first message sent by a first clock device, the first message comprising first clock level information, and the first clock level information being deter...  
WO/2013/078926A1
A method and communication system for obtaining time deviation between a primary device and a secondary device in case of fiber optic asymmetry, the method comprising: the primary device transmits a first packet to the secondary device v...  
WO/2013/023655A3
The invention relates to a circuit arrangement (A) and to a corresponding method, using single-ended signals based on logic levels and differential, in particular common mode based signals, in which a full duplex data transmission is pos...  
WO/2013/079365A1
The invention relates to a method for synchronizing clocks (1, 2) in nodes of a vehicle network of a motor vehicle, wherein the nodes communicate with one another by means of a communication protocol that is not synchronized per se, and ...  
WO/2013/023652A3
The invention relates to a circuit arrangement (A) and to a corresponding method which use both single-ended signals based on logic levels and differential, in particular common-mode-based signals, to continually transmit a serialized si...  
WO/2013/078100A1
A slave communication device may transmit a packet to the master communication device, with the packet including a transmission time field and a correction field. The transmission time field may contain a value indicative of an approxima...  
WO/2013/023654A3
The invention relates to a circuit arrangement (A) and to a corresponding method, using single-ended signals based on logic levels and differential, in particular common mode based signals, in which the power consumption required for the...  
WO/2013/076796A1
This frequency switching circuit includes: a first counting circuit which counts the number of pulses of a first clock signal in a predetermined period in order to generate a first count value; a second counting circuit which counts the ...  
WO/2013/023651A3
The invention relates to a circuit arrangement (A) and to a corresponding method which use both single-ended signals based on logic levels and differential, in particular common-mode-based signals, to continually transmit a serialized si...  
WO/2013/023653A3
The invention relates to a circuit arrangement (S, E) and to a corresponding method, using single-ended signals based on logic levels and differential, in particular common mode based signals, in which a serialized signal is continually ...  
WO/2013/074159A1
A system and method for a radio controlled clock receiver adapted to extract timing and time information from a phase modulated signal. The official time signal is broadcast from a central location using a modulation scheme that adds pha...  
WO/2013/071807A1
A method, a system and an apparatus for implementing hybrid networking of multiple clock synchronization technologies. A master clock and one or more slave clocks are set for a synchronization device serving as both a clock synchronizati...  
WO/2013/071506A1
A method, apparatus and computer program product are provided for generating Reference Signals utilized in downlink tracking of an unlicensed band. A method and apparatus may determine whether carriers of an unlicensed band secondary com...  
WO/2013/070241A1
An embodiment may include circuitry that may generate and/or use, at least in part, at least one descriptor to be associated with at least one packet. The at least one descriptor may specify at least one transmission time at which the at...  
WO/2013/069176A1
A transmitter (90) is connected to a master device, and wirelessly transmits timing packets sent from the master device to a receiver. The transmitter (90) comprises: an input means (91) that receives the input of a timing packet from th...  
WO/2013/070797A1
A physical layer device provides both timestamp processing and security processing. The timestamp processing may be PTP processing according to IEEE Std. 1588 and/or OAM processing according to ITU-T Recommendation Y.1731. The security p...  
WO/2013/065875A1
There is provided a wireless communication which is applicable to a wireless sensor using a TDMA method, has low power consumption, and is strong on hindrance due to wireless interference. A tributary station includes a communication blo...  
WO/2013/066532A1
A method and receiving device are provided that determine a synchronization byte in a plurality of transport stream packets, wherein the synchronization byte has a predetermined synchronization value. The method/receiving device receives...  
WO/2013/065208A1
In the present invention, a timing recovery circuit is provided with the following: a clock generating circuit (10) for generating clock signals of different cycles by using first and second operation modes; phase compensation circuits (...  
WO/2013/067200A2
A serial bit stream having a given bit per second rate is received and distributed to a plurality of phase shifted samplers. A multi-phase sampling trigger is generated at a rate lower than the given bit per second rate, and each of the ...  
WO/2013/061272A1
The invention relates to a data communication system (100) and a method that can particularly be applied for communicating data from a medical instrument like a catheter or a guide-wire via a high-speedlink (101). The system (100) compri...  
WO/2013/063500A2
Exemplary embodiments are directed to data and clock recovery in NFC transceivers. A transceiver may include a phase-locked loop configured to recover a clock from a received input signal in a first mode and enable for oversampling of an...  
WO/2012/136161A3
Disclosed in the present invention are a heartbeat synchronization method and device, said method comprising: obtaining an interval list and a timing list; obtaining, according to the interval list, the length of a heartbeat interval; ob...  
WO/2013/053256A1
A method and apparatus for determining validity of a clock synchronization source device. The method comprises: a slave clock device receiving an announce packet and a sync packet sent by a clock source device, and sending a delay_req pa...  
WO/2012/126420A3
The embodiments of the present invention relate to a data and clock recovery module and a data and clock recovery method. The method includes: performing phase adjustment on a clock signal generated on the basis of the reference frequenc...  
WO/2013/055965A1
Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a f...  
WO/2013/051445A1
The disclosure relates to: a frequency difference detection device capable of synchronizing oscillation frequencies with a master device on a network, with high precision; a frequency difference detection method; and a program. This freq...  
WO/2013/051446A1
The present disclosure relates to a time control device, time control method, and program, with which it is possible to highly precisely synchronize time information with a master apparatus on a network. The disclosed time control device...  
WO/2013/051447A1
The disclosure relates to: a time control device capable of synchronizing, with high precision, time information with a master device on a network; a time control method; and a program. This time control device comprises: a first calcula...  
WO/2013/050742A1
This invention relates to the problem of communicating information from a device such as a PC ('101'), having an extensive user interface including visual display screen, to a portable electronic device with limited user interface ('201'...  
WO/2013/048377A1
Systems, devices and methods are described including specifying a jitter response control parameter, receiving multiple timestamp pairs. A maximum jitter of the timestamp pairs may be determined along with an elapsed time, and a clock fr...  
WO/2013/047728A1
[Problem] To simplify the operation of transmitting content data and a clock signal in a system that transmits content data from a content playback device to an output device. Also, to prevent degradation in the sound quality or image qu...  
WO/2013/047450A1
Mobile radio devices are disposed at the front and rear ends of a mobile body in such a manner that the mobile radio devices can communicate. At least one of fixed radio devices is used as a synchronization base station. The other radio ...  
WO/2013/041147A1
A method in a QAM receiver (100) for performing timing recovery. The QAM receiver (100) is configured to receive a sequence of symbols. Each symbol is represented by a respective IQ pair comprising a respective inphase component I and a ...  
WO/2013/042516A1
Provided is a technique that transmits frame synchronization information converted into a TS packet format. A synchronization signal generating device according to an embodiment of the present invention is provided with: a transmission c...  
WO/2012/160105A9
Embodiments of the present invention provide an apparatus for synchronizing a data handover between a first clock domain and a second clock domain. The apparatus includes a calculator, a synchronization pulse generator, a phase informati...  
WO/2013/039837A1
A method is provided for synchronizing a first radio unit with a second radio unit associated with an all outdoor radios system, the method including: receiving, at the first radio unit and the second radio unit, respectively, a communic...  
WO/2013/038978A1
The purpose of the invention is to provide a signal transmission device capable of transmitting a plurality of data without an increase in cost. The signal transmission device (2) is provided with a transmitter (3), a receiver (4), and a...  
WO/2013/038562A1
One aspect of the present invention is a transmitting system, which has a data transmitting apparatus (10) that transmits data at a first speed, and a data receiving apparatus (20) that receives the data using a plurality of clocks havin...  
WO/2013/036401A1
Aspects of the disclosure provide a signal processing circuit (1130) that includes a processing path (1140) configured to process an electrical signal to produce input data samples, and a feed-forward correction module (1160) configured ...  
WO/2012/170921A3
A method for transmitting data on a data line of a two-wire bus wherein the bus includes a data line and a clock line includes the step of pulling the data line of the two-wire bus low to define a start condition. Next, a first group of ...  
WO/2013/033108A1
A system and method of retaining synchronization in a shared medium communications network. Synchronization is maintained between colliding transmitters and receivers by providing a Collision Based Inter Frame Space (CBIFS) which is a ti...  
WO/2013/031463A1
[Problem] To provide an optical transceiver and others that allow for easy performance of timing adjustment between SDA and SCL signals without loss of removability. [Solution] An optical transceiver (10) comprises: an I2C slave circuit ...  
WO/2013/031476A1
A transmission/reception system (1A) comprises a transmission device (10A) and reception device (20A). The transmission device (10A) comprises an encoding unit (11), serializer (12) and transmission unit (13). The reception device (20A) ...  
WO/2013/029441A1
Disclosed in the embodiments of the present invention are a method and device for clock synchronization. The method comprises the following steps: slave clock equipment simultaneously carries out protocol message interactions with multip...  
WO/2013/009131A3
The present invention discloses an apparatus and a method for transmitting a packet and an apparatus and a method for receiving a packet, based on a timing model of an MPEG media transport (MMT) system, which is integrated by considering...  
WO/2013/023530A1
An implementation method and device for automatically detecting the asymmetry time delay of a 1588 link. The implementation method includes: operating a 1588 time synchronization protocol and calculating a time deviation value; amending ...  
WO/2013/001095A9
A signal propagation system for communicating timing information comprises a processing resource (300) arranged to generate a first timing signal for communicating the timing information, the first timing signal having a first frequency ...  
WO/2013/023538A1
Disclosed are a synchronization network clock maintenance method and device. In the above method, a query request is regularly sent to the clock units of all the devices in a network; operating state data from each clock unit is received...  

Matches 901 - 950 out of 39,241