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WO/2020/185248A1 |
A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.
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WO/2020/183738A1 |
An exclusive NOR (XNOR) gate includes an inverter, a first resistive switch whose first terminal is connected to an input terminal of the inverter, and a second resistive switch whose first terminal is connected to an output terminal of ...
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WO/2020/180247A1 |
Biocompatible transient switching memory devices and methods for their fabrication are provided. In accordance with one aspect, a memory device is provided. The memory device includes a layer comprising tungsten, a lower electrode compri...
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WO/2020/179199A1 |
In this non-volatile memory device (100), inside a storage area (60), a first lower layer metal wiring (20), a bottom plug (30), a variable resistance element (40), a top plug (32), and a first upper layer metal wiring (23) are formed in...
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WO/2020/180248A1 |
Biodegradable threshold switching devices and methods for their fabrication are provided. In accordance with one aspect, a biodegradable threshold switching device includes a bottom electrode, a top electrode, and a switching layer sandw...
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WO/2020/179006A1 |
A nonvolatile semiconductor storage device according to an embodiment of the present invention is provided with: a plurality of first wiring layers that extend in a first direction and that are aligned along a second direction intersecti...
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WO/2020/131054A9 |
A high-voltage switch, whose operation leverages the speed of electrons to generate the "on" time of the pulse in combination with the speed of light to generate the "off" time of the pulse, is described. In one example, the high-voltage...
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WO/2020/172499A1 |
Resistive switching devices that contain lithium, including resistive switching devices containing a lithium titanate, and associated systems and methods are generally described. In some cases, the resistive switching device contains a l...
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WO/2020/166073A1 |
According to an embodiment, a nonvolatile semiconductor storage device is provided with: a plurality of first wiring layers extending in a first direction; a plurality of second wiring layers extending over the plurality of first wiring ...
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WO/2020/161562A1 |
A resistive memory structure is provided. The resistive memory structure includes a vertical fin on a substrate, wherein the sidewalls of the vertical fin each have a {100} crystal face. The resistive memory structure further includes a ...
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WO/2020/161454A1 |
Disclosed is a method for the fabrication of a correlated electron material (CEM) device to an comprising: forming a layer of a conductive substrate on a substrate; forming a layer of a correlated electron material on the layer of conduc...
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WO/2020/159214A1 |
The present invention provides a selector device and a cross-point memory including same. The selector device is provided with a lower electrode. A polycrystalline metal oxide film is positioned on the lower electrode, the polycrystallin...
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WO/2020/153618A1 |
Disclosed is a bi-directional two-terminal phase-change memory device using a tunneling thin film and a method of operating same. According to one embodiment, a phase-change memory device comprises: a first electrode; a second electrode;...
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WO/2020/154123A1 |
A method for fabricating a plurality of resistive random access memory (RRAM) cells includes providing a substrate including a memory medium arranged on an underlying layer; creating channel holes in the memory medium having a first crit...
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WO/2020/154028A1 |
An exemplary semiconductor incorporates phase change material MoxW1-xTe2 that may be the semiconducting channel or may be part of a control terminal/gate of the semiconductor. The phase change material selectably being in one of metal an...
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WO/2020/145253A1 |
A switching element that has reduced switching voltage and leakage current and that demonstrates high reliability and low power consumption is achieved as a result of comprising: a first insulating layer in which first wiring mainly cons...
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WO/2020/136974A1 |
This resistance-variable nonvolatile memory element (20) comprises: a first electrode (2); a second electrode (4); and a resistance-variable layer (3) disposed between the first electrode (2) and the second electrode (4) and having a res...
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WO/2020/138975A1 |
A memory device is provided. The memory device may comprise: a first electrode; a resistance change layer placed on the first electrode and containing an alkali metal and a transition metal; and a second electrode placed on the resistanc...
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WO/2020/133137A1 |
Disclosed are a threshold switch device based on an organic-inorganic hybrid perovskite and a preparation method therefor, belonging to the field of data storage. The threshold switch device comprises a bottom electrode (703), a dielectr...
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WO/2020/131397A1 |
Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques...
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WO/2020/130276A1 |
Disclosed is an electrolytic bismuth calcium iron oxide having high oxygen-deficient ion mobility. One example of the present invention may provide an oxygen-deficient electrolytic material comprising bismuth calcium iron oxide (Bi1-xCax...
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WO/2020/124929A1 |
Disclosed in the present invention is a phase change memory, comprising, from bottom to top, a substrate, a doping layer, a diode and a phase change resistor, an upper part of the substrate being the doping layer, and the doping layer an...
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WO/2020/130343A1 |
The present invention provides a selection device and a memory device including same. The selection device according to an embodiment of the present invention has a high reliability and a high selection ratio, and thus can provide a high...
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WO/2020/119738A1 |
A memristor and a method for manufacturing the same. The memristor comprises a substrate (1) and a first electrode functional layer (21) and a second electrode functional layer (22) disposed on the substrate and spaced apart from each ot...
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WO/2020/112544A1 |
Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A component of a memory cell, such as a selector device, storage device, or self-selecting memory device, may be made ...
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WO/2020/109991A1 |
The invention relates to a non-volatile resistive random access memory (ReRAM), a non-volatile ReRAM composition and to a method for manufacturing a non-volatile non-volatile ReRAM. The ReRAM includes a first electrode, a second electrod...
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WO/2020/109753A1 |
Subject matter disclosed herein relates to fabrication of a correlated electron material (CEM) switch (302). In particular embodiments a method include forming a structure (160, 170, 180) on a first portion of a substrate (262) while mai...
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WO/2020/111752A2 |
A semiconductor device having a negative differential transconductance characteristic according to an embodiment of the present invention comprises: a substrate; a gate electrode formed on the substrate; an insulation layer formed on the...
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WO/2020/099584A1 |
The invention describes a memory device which combines a switchable resistive element and a superconductor element electrically in parallel. The switchable resistive element comprises an active material, which is switchable between first...
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WO/2020/089786A2 |
There is provided a planar graphene oxide (GO)-based device comprising of multiple resistance state elements in response to an applied voltage and wherein the multiple resistance state elements mimic neural synapse behaviour. The device ...
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WO/2020/091307A1 |
One embodiment of the present invention is a variable low resistance line memory device and a method for operating same. Disclosed is a memory device and a method for operating same, the memory device comprising: a base including a spont...
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WO/2020/084703A1 |
The present invention is a method for producing an OTS device in which a first conduction part, an OTS part that is formed of a chalcogenide, and a second conduction part are sequentially stacked on an insulating substrate. This producti...
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WO/2020/082023A1 |
A Re RAM device manufactured using 2-D Si2Te3(silicon telluride) nanowires or nanoplates. The SiaTeg nanowires exhibit a unique reversible resistance switching behavior driven by an applied electrical potential, which leads to switching ...
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WO/2020/079429A1 |
Subject matter disclosed herein relates to fabrication of a correlated electron material (CEM) switch. In particular embodiments, formation of a CEM switch (300) includes removing of an exposed portion of a CEM film (170) to form an expo...
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WO/2020/076759A1 |
A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate ele...
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WO/2020/072885A1 |
Apparatus, systems, and methods for resistive switching are generally described.
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WO/2020/056923A1 |
A three-dimensional stacked phase change memory and preparation method therefor. The preparation method specifically comprises: preparing, on a substrate, first horizontal electrodes having spaces therebetween; preparing, in the spaces b...
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WO/2020/045845A1 |
Disclosed are a two-terminal phase-change memory device and an operation method therefor. According to one embodiment, a phase-change memory cell, used in the phase-change memory device, comprises: an intermediate layer formed from a P-t...
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WO/2020/041047A1 |
Methods, systems, and devices for operating memory cell(s) using transition metal doped GST are described. As discussed herein, a composition including germanium (Ge), antimony (Sb), tellurium (Te), and at least one of yttrium (Y) and sc...
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WO/2020/041011A1 |
Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a re...
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WO/2020/037241A1 |
The disclosed embodiments relate to the design of a new type of transistor called a "field-effect bipolar transistor" (FEBT). This FEBT includes a substrate, which comprises a body of the FEBT. It also includes a source comprising an N+ ...
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WO/2020/030887A1 |
A method for the manufacture of a correlated electron material device which method comprises forming a conductive substrate and forming a layer of a correlated electron material on the conductive substrate, wherein the forming of the cor...
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WO/2020/030901A1 |
The disclosed non-volatile memory cell comprises a storage layer of an electrically insulating polarisable material in which data is recordable as a direction of electric polarisation, preferably of ferroelectric material, arranged betwe...
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WO/2020/024216A1 |
Disclosed in the present invention is a resistive random access memory, which is characterized in that the resistive random access memory successively comprises, from bottom to top, a lower electrode layer, a ferroelectric material layer...
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WO/2020/024221A1 |
Provided in the embodiments of the present application are a preparation method and preparation device for a memristor electrode material, and a memristor electrode material; the preparation method comprises: using a reactive sputtering ...
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WO/2020/018336A1 |
Thermally activated memristors from solution-processed two-dimensional (2D) semiconductors, fabricating methods and applications of the same. The memristor includes a semiconductor film formed on a nanoporous membrane, and at least two e...
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WO/2020/012916A1 |
[Problem] The present invention addresses the problem of providing a laminate structure in which the atomic arrangement is highly stable, a method for manufacturing the laminate structure, and a semiconductor device in which the laminate...
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WO/2020/001328A1 |
Disclosed in the present invention is a high performance memristor device based on the oxygen concentration gradient of a metal oxide, and the preparation thereof, the units of the memristor device comprising from top to bottom an upper ...
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WO/2020/005331A1 |
A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposit...
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WO/2020/005371A1 |
A layout is presented for a ReRAM memory cell array including rows and columns of ReRAM cells, each ReRAM cell is in a row and column of ReRAM cells. Each ReRAM cell includes a ReRAM device. A first transistor is coupled between the ReRA...
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