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JP4077483B2 |
A feedback path ( 307 ) is formed between an output ( 310 c) of a fixed divider ( 305 ) and a control terminal ( 310 b) of an inverting/noninverting unit ( 304 ). A connection device ( 306 ) is arranged on the feedback path ( 307 ). The ...
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JP2008035452A |
To provide a clock generating circuit in which an output clock of a weak side band can be obtained by relaxing periodicity even on such an output frequency generation condition that periodicity may occur.A counter 22 counts the number of...
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JP4046528B2 |
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JP4044819B2 |
The dual-modulus prescaler circuit for a frequency includes several dividers-by-two of the asynchronous type, connected in series, a phase selector unit (11) inserted between two of the dividers-by-two (10, 12a) and a control unit for su...
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JP4038222B2 |
In a statistic counter device comprising a plurality of statistic counters which count statistic information, in order to reduce a hardware scale and power consumption by dynamically controlling a bit number of the statistic counters, a ...
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JP3998676B2 |
A bi-directional shift register circuit comprising, a plurality of shift register stages, each having an input and an output terminal, and a bi-directional shift controller circuit associated with each of said shift register stages is di...
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JP3985588B2 |
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JP3980203B2 |
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JP2007243618A |
To provide a frequency divider circuit for reducing the ratio of a large power consumption circuit, such as a buffer circuit, and avoiding the increase of power consumption due to a limited layout by placing the frequency divider circuit...
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JP2007235960A |
To provide an integrated circuit device which generates a plurality of drowsy clock signals having different phases. The integrated circuit device includes a phase synchronizer configured to output a plurality of clock signals having dif...
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JP2007235578A |
To provide a clock generation circuit which can be commonly used in a plurality of different broadcasting systems and achieve simplification and miniaturization of a circuit composition. While using a voltage controlled oscillator 11 wit...
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JP2007215213A |
To provide a method for multiple-phase clock generation. In one embodiment, a multiple-stage voltage controlled oscillator ("VCO") (302) transmits a plurality of clock phases (ck0-ck5) to a clock divider (304) which produces the desired ...
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JP3962455B2 |
To provide a method for reducing the power consumption of a digital circuit while maintaining an operation with a high frequency. This is a clock mechanism which uses an outside clock signal with a frequency F, and generates an inside ma...
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JP2007208589A |
To enable an n-division harmonic frequency divider (wherein, n is an integer of two or above) to be easily configured. The harmonic frequency divider 30 includes a harmonic mixer 32, a resonance circuit 34, and a buffer 36. The harmonic ...
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JP2007522712A |
A non-quasistatic MOS frequency divider circuit uses a phase lock loop configuration including an antenna coil to induce a differential input signal, an antenna resonating capacitor, a rectifier, a voltage controlled ring oscillator, a p...
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JP3949995B2 |
To provide a counter circuit capable of forming a plurality of pulse signals of different periods, without increasing the circuit scale. The counter circuit comprises an initial value register single port RAM 5, having initial value regi...
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JP3940877B2 |
To provide a pulse output device that eliminates the need for error correction of an oscillation frequency and can realize synchronization with an execution period of (input data from) an external processing unit, such as a CPU and that ...
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JP3941376B2 |
To provide a signal distributing device and a signal distributing method by which waveform deterioration or delay, etc., caused by a wiring length between printed boards is hardly received in a unit where the multiple printed substrate a...
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JP3935901B2 |
To provide a programmable low-power high-frequency divider circuit. A fast latch includes: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage wherein a first input of the clocked inverter sta...
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JP3930773B2 |
To provide a frequency correction circuit for precisely correcting a clock signal of an oscillation frequency with a simple structure without adjusting the oscillation frequency in an oscillation circuit. Into the TBC(time-base counter)1...
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JP3918276B2 |
To provide a failure detecting method capable of detecting failure of a timer and a bus line between a timer and capture resistor at low cost without enlarging the scale of a circuit for failure detection, and not requiring an interrupt ...
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JP2007074434A |
To prevent erroneous latch of a count value read by a host control part.When (start timing of) a host control part latch signal 15 from the host control part 23 matches to sampling timing of a sampling clock 18, a reading register latch ...
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JP3891877B2 |
To change the average frequency of a clock signal independently from a reference clock signal. A reference clock signal generating circuit 1 generates a reference clock signa. A dividing circuit 2 divides the reference clock signal by a ...
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JP3893902B2 |
To provide an image forming device and a method for updating information in the device by which count data is updated speedily to a storage element such as a semiconductor memory. The count data is constituted by two-byte gray codes. The...
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JP3868505B2 |
A counter circuit includes a series of registers driven by two phase shifted clocks. A clock generator in the counter circuit generates four asymmetrical clock signals to drive each of the registers. The registers are formed from input a...
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JP3869428B2 |
To provide a counting device which satisfies fail safe counting performance not performing rash counting output in a failure time, and is excellent in reliability. The device comprises a counter 100 which generates an output, when counti...
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JP3857916B2 |
To make it possible to be operated with a small signal amplitude and reduce power consumption in a two-modulus prescaler circuit available for a frequency synthesizer or the like. The prescaler circuit is provided with n pieces of (n≥3...
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JP3850367B2 |
To change a frequency dividing ratio of a clock signal without enlarging a circuit scale. Whenever a reference clock signal is inputted from a reference clock signal source 20, output signals of stages Q2 and Q3 of a counter changing out...
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JP2006314134A |
To provide a high-speed counter circuit which produces digital counts, with a plurality of bits to control the timing of operations in a memory device.A counter circuit includes a series of registers driven by two phase shifted clocks. A...
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JP3847150B2 |
To provide a semiconductor integrated circuit, which can measure accurately frequencies and jitters of the built-in PLL (phase locked loop), and measurement method for its jitters. A master clock signal MCK obtained by N multiplication o...
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JP3825722B2 |
To provide a semiconductor circuit device for making it unnecessary to synchronously arbitrate an interface between a block synchronizing with a source clock and an integrated circuit part operating with a frequency different from the so...
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JP2006222515A |
To provide a technology for preventing mis-update of registers in a real time clock module.The real time clock module is configured for the purpose of suppressing occurrence of hazard by including: a first register (43) capable of captur...
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JP2006201856A |
To exclude the erroneous update of a register in a real time clock module.This semiconductor integrated circuit is configured of a real time clock module (16) for performing a count operation based on a first clock signal and a CPU to be...
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JP2006174098A |
To reduce a circuit scale in a frequency divider circuit capable of generating a dividing clock at an arbitrary division ratio.The frequency divider circuit comprises a counting circuit and a comparison circuit. The counting circuit coun...
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JP2006162257A |
To provide an operating mode setting circuit for surely setting a test mode of various kinds, even when a manual evaluation tool is used.A logic circuit 11 is reset by a system reset signal SRST, while resetting FFs 17 and 18 and a count...
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JP3789063B2 |
To obtain a symbol clock regeneration circuit with a simple configuration that can conduct high-speed phase locking and generates a stable recovery symbol clock signal even in the case that a carrier frequency error is high and a phase o...
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JP3779500B2 |
To provide a burst-type RAM device having a double-data speed method and consisting of improved address generating and decoding circuits, and address generating method thereof. A burst-type RAM device has a memory cell array for storing ...
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JP3773250B2 |
To provide a synthesizer and a signal analyzer which perform edge arrangement of exact and high resolution without necessity of system clock of frequency very higher than frequency of a synthetic clock signal. It comprises a system clock...
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JP3771223B2 |
To provide a timing adjuster in which a required time can be set accurately without using a capacitor for adjusting the time and drift of a set adjusting time is reduced. An input signal Vina is converted into a digital signal by an AD c...
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JP2006513507A |
A digital counter that uses non-volatile memories as storage cells, wherein the storage cells are sub-divided into two groups, one for the implementation of a rotary counter that keeps track of the less significant part of the count and ...
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JP2006080917A |
To provide a current mode type input logic gate circuit which can lower minimum power supply voltage without sacrificing rapidity and operates at lower voltage (e.g., ≤1 V), a latch circuit, a flip-flop circuit, a frequency dividing ci...
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JP3732556B2 |
To improve considerably a clock skew between a signal via a through- path and a frequency divided signal via a frequency divided path from a same clock signal source in the clock supply circuit. The circuit is provided with a clock signa...
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JP3727206B2 |
To provide a clock changing circuit which changes clocks even though clocks before and after changing include jitter and also, control input signals for write and read are not inputted from the outside. This circuit detects a clock CLK-1...
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JP3715290B2 |
To improve qualities of a video controller and a product incorporated with the video controller and to reduce a required effort and cost. This video synchronization testing method comprises: a process for constructing a display mode tabl...
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JP3714875B2 |
To provide a gray code counter, with which skip counting is enabled and the number of bit transitions in skip counting is two at all the time. This gray code counter is provided with a gray code counter 2 in the configuration of 5 bits f...
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JP2005283408A |
To provide a counting device for further contracting a measuring error of a predetermined period.A level of a clock signal CLK in rise and descent edge of a signal TERM being a measuring object of the predetermined period is detected by ...
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JP3703347B2 |
To provide a frequency divider circuit from which a frequency division ratio of 2 over odd numbers with a simple circuit configuration. The frequency divider circuit comprises a flip-flop multi-stage circuit G consisting of n-sets of fli...
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JP3691310B2 |
To provide a frequency measuring circuit which provides high measurement precision even in the case of a short counting period or a reference clock having a low frequency. In the frequency measuring circuit, plural frequency measuring un...
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JP2005233885A |
To provide a meter controller capable of shortening the times of second clock oscillation and of estimating the oscillation time.The meter controller is provided with a reference clock oscillator which generates a reference clock for mea...
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JP3688683B2 |
To generate a precise fraction frequency division signal irrespective of precision of a decimal part of a frequency-divided number. A cumulative adder 7 performs cumulative addition of a decimal value f set in an f setting part 8 in resp...
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