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Matches 1 - 50 out of 4,906

Document Document Title
WO/2021/032859A1
The invention relates to a passive micromechanical counter (10) for counting and storing a number of mechanical pulses, comprising at least one storage cell (12). The storage cell (12) comprises a cell input (14), a latching mechanism (1...  
WO/2021/028195A1
A circuit arrangement for charge integration comprises an input (1) for applying a signal representing charge pulses, an output (2) for providing an integrated signal and an integrating circuit (3) connected between the input (1) and the...  
WO/2021/002051A1
The present invention provides a counter unit (10) that supports, in a plurality of output devices, both a case where there is no problem in a state in which common signal terminals or power supply terminals are connected by common wirin...  
WO/2020/230411A1
Provided is a counter unit capable of supporting any output apparatus of single-phase output, two-phase output, or three-phase output without waste. A counter unit (10) is provided with: a plurality of signal input terminals to which pul...  
WO/2020/223105A1
A frequency divider includes a circuit that receives an input clock signal having a period T on an input port thereof and generates an output clock signal on an output port thereof having a period MT in response to a control signal speci...  
WO/2020/176556A1
Amplitude-modulated (AM) signals spanning a spatial wide area can be efficiently detected using a slowly scanning optical system. The system decouples the AM carrier from the AM signal bandwidth (or carrier uncertainty), enabling Nyquist...  
WO/2020/101761A1
A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit...  
WO/2020/091985A1
Various embodiments relate to multi-modulus frequency dividers, devices including the same, and associated methods of operation. A method of operating a multi-modulus divider (MMD) may include determining a common state for the MMD, wher...  
WO/2020/084407A1
The present invention reduces the power used by a semiconductor device. The present invention is a semiconductor device having a latch circuit formed by a dynamic circuit. The latch circuit has: a first circuit having a decoding function...  
WO/2020/086269A1
A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in...  
WO/2020/037485A1
Provided in the present application are a detection circuit, a method, a chip, and a device. The circuit comprises a synchronization module, and a detection module connected to the synchronization circuit, wherein the synchronization mod...  
WO/2020/013819A1
A fail-safe counter evaluator (200) is provided to insure proper counting operations by fail-safe counters. The failsafe counter evaluator comprises a first microprocessor (205-1), a first counter (212-1), a second counter (212-2), a sec...  
WO/2018/089121A3
A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The...  
WO/2018/213399A1
An integrated circuit device for reservoir computing can include a weighted input layer, an unweighted, asynchronous, internal recurrent neural network made up of nodes having binary weighting, and a weighted output layer. Weighting of o...  
WO/2018/089121A2
A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The...  
WO/2018/052982A3
Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may...  
WO/2017/146833A3
The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first...  
WO/2017/146833A2
The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first...  
WO/2017/048419A1
Systems and methods for dividing input clock signals (CLKin) by programmable divide ratios (N) can produce output clock signals (CLKdiv) with the delay from the input clock signal to the output clock signal independent of the value of th...  
WO/2016/187333A1
Systems and techniques are provided for a multichannel waveform synthesis engine. A phase counter module counts to a value corresponding to a number of phases available, outputs a phase counter value indicating a current phase, and reset...  
WO/2016/089291A1
An electronic latch circuit (100), a 4–phase signal generator, a multi–stage frequency divider and a poly–phase signal generator are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first...  
WO/2016/089292A1
The present invention relates to a combiner latch circuit and a latching system for generation of one phase differential signal pair or two phase differential signal pairs. The scope of the applications ranges from division and frequency...  
WO/2016/089275A1
An electronic latch circuit (100) and a multi−phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third out...  
WO/2016/074350A1
The present invention provides a burr removing method and apparatus for an optical signal loss signal. The present invention adopts the technical solution of: when detecting that an online signal output by an optical module changes from ...  
WO/2016/076798A1
A regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the trans...  
WO/2016/037118A1
In described examples of providing multiple clock frequencies for an integrated circuit having a plurality of modules, a reference clock signal (fin) is frequency division processed (401) to generate sub-divider outputs of fin divided by...  
WO/2016/007552A1
A circuit (100) includes an amplifier output stage (124, 164) that includes a high switch (134, 174) and a low switch (136, 176) that generates a pulse width modulated (PWM) output signal to provide a load current to a load in response t...  
WO/2015/116813A1
A system may have a digital period divider generating an output signal that is proportional to an angle defined by a rotational input signal and an interval measurement unit determining an interval time of an interval defined by succeedi...  
WO/2015/112609A1
A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a det...  
WO/2015/065683A1
Certain aspects of the present disclosure provide apparatus for producing an output signal having a duty cycle of 50% and a frequency that is one third that of an input signal. One example frequency dividing circuit for producing such an...  
WO/2011/100032A8
Conventional retimers generally consume too much power, are too noisy, and are too large. Additionally, phase noise and jitter are generally a function of retiming. In a described apparatus, a preconditioner 204 has logic 206 mapped to o...  
WO/2014/209715A1
A frequency divider (300) with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit (310a, 310b) and at least one duty cycle adjustment circuit (320a, 320b)...  
WO/2014/202230A1
The present invention relates to an apparatus and a method for generating RF signals, the pulse width and pulse position of which are modulated. The apparatus comprises a digital device (2, 3) which is intended to generate different phas...  
WO/2014/164376A1
A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives...  
WO/2014/095792A1
A synchronizer circuit 200 comprises a first flip-flop operated with a first clock signal C1, the first flip-flop being configured to read a data item at a first sampling point correlating with a first edge of a first edge type of the fi...  
WO/2014/066402A1
In various embodiments, an integrated circuit is disclosed. In one embodiments, the integrated circuit comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area com...  
WO/2014/063316A1
The present invention discloses a pulse frequency measurement device and method and a control system, the device including: a hardware counter configured to perform a counting operation on an input pulse sequence to output a counting res...  
WO/2014/043339A1
A divider (200) apparatus includes latches ( 202-1,202-2) that are coupled in series with one another in a ring configuration. Each latch includes a tri- state inverter (Q9-1Q12), a first resistor-capacitor network (R1, C1), and a second...  
WO/2013/185960A3
The invention relates to a digital sensing circuit (100) for a secondary clock signal (204) to be monitored for clock failure with the aid of a primary clock signal (202), comprising a flip-flop (102) which has a clock input (108), a dat...  
WO/2013/082611A3
A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a comp...  
WO/2013/185960A2
The invention relates to a digital sensing circuit (100) for a secondary clock signal (204) to be monitored for clock failure with the aid of a primary clock signal (202), comprising a flip-flop (102) which has a clock input (108), a dat...  
WO/2013/179089A1
A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged t...  
WO/2012/038882A9
A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory contro...  
WO/2013/155352A1
A frequency divider circuit having two stages of transistors has improved performance at low supply voltages. The circuit may include cross-coupled PMOS (112a, 112b) and NMOS transistors (114a, 114b), in which the input signal to be freq...  
WO/2013/128334A1
There is provided a method of controlling a CPRI monitor port of a remote radio equipment following a powering cycle. Access to the CPRI monitor port is first detected. An absence timer decrementing process is started when the CPRI monit...  
WO/2013/098127A1
A high speed clock frequency divider circuit is provided that uses a first shift register loop-back circuit and a second shift-register loop-back circuit to shift a predetermined array of bits therethrough. The first shift register loop-...  
WO/2012/042044A8
High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMO...  
WO/2013/060134A1
The present invention provides a time-resolved single-photon or ultra-weak light multi-dimensional imaging system and method. In one aspect, to achieve coarse time resolution, the present invention provides a time-resolved single-photon ...  
WO/2013/057060A1
A programmable high-speed frequency divider architecture is provided to provide a substantially 50% duty cycle signal output regardless of whether the division ratio is odd or even. The programmable frequency divider circuit receives an ...  
WO/2013/048525A1
A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division...  

Matches 1 - 50 out of 4,906